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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Decrease log level
Date: Thu, 5 Mar 2020 15:55:34 +0200	[thread overview]
Message-ID: <20200305135534.GN13686@intel.com> (raw)
In-Reply-To: <08c5b5fb8abcd40b86b68365f67bec851ec6c6d6.camel@intel.com>

On Thu, Mar 05, 2020 at 08:55:31AM +0000, Lisovskiy, Stanislav wrote:
> On Tue, 2020-03-03 at 03:08 +0530, Swati Sharma wrote:
> > Converting error to debug print if sink fails to configure scrambling
> > or
> > TMDS bit clock ratio. In this case, we are timing out while disabling
> > the scrambling and setting the SCDC ratio, as there is no response
> > to the I2C SCDC write from the sink device. Error isn't due to
> > something
> > wrong done from driver side.
> > 
> > Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Pushed to dinq. Thanks for the patch and review.

> 
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 284219da7df8..457ca88cd277 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3564,8 +3564,9 @@ static void intel_enable_ddi_hdmi(struct
> > intel_encoder *encoder,
> >  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> >  					       crtc_state-
> > >hdmi_high_tmds_clock_ratio,
> >  					       crtc_state-
> > >hdmi_scrambling))
> > -		DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink
> > scrambling/TMDS bit clock ratio\n",
> > -			  connector->base.id, connector->name);
> > +		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to configure
> > sink "
> > +			      "scrambling/TMDS bit clock ratio\n",
> > +			       connector->base.id, connector->name);
> >  
> >  	/* Display WA #1143: skl,kbl,cfl */
> >  	if (IS_GEN9_BC(dev_priv)) {
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2020-03-05 13:55 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-02 21:38 [Intel-gfx] [PATCH] drm/i915/display: Decrease log level Swati Sharma
2020-03-02 22:54 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
2020-03-02 23:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-03 11:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-05  8:55 ` [Intel-gfx] [PATCH] " Lisovskiy, Stanislav
2020-03-05 13:55   ` Ville Syrjälä [this message]

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