From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter
Date: Tue, 10 Mar 2020 22:44:19 +0200 [thread overview]
Message-ID: <20200310204419.GT13686@intel.com> (raw)
In-Reply-To: <468947d5c7842d7e30ec0b6881a41e237aff4fdd.camel@intel.com>
On Tue, Mar 10, 2020 at 02:54:12PM +0000, Lisovskiy, Stanislav wrote:
> On Tue, 2020-03-10 at 16:32 +0200, Ville Syrjälä wrote:
> > On Mon, Mar 09, 2020 at 06:11:57PM +0200, Stanislav Lisovskiy wrote:
> > > We need to start passing memory latency as a
> > > parameter when calculating plane wm levels,
> > > as latency can get changed in different
> > > circumstances(for example with or without SAGV).
> > > So we need to be more flexible on that matter.
> > >
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
> > > 1 file changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 8375054ba27d..c7928c870b0a 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct
> > > intel_crtc_state *crtc_state,
> > > int color_plane);
> > > static void skl_compute_plane_wm(const struct intel_crtc_state
> > > *crtc_state,
> > > int level,
> > > + u32 latency,
> >
> > So you didn't change the types?
>
> Yes, I saw your comment there - and looked into this, however I just
> wondered, does it make any sense do to that. The reason is because
> skl_latency is anyway defined as u16 in i915_drv.h, just as pri/spr/cur
> latencies, so wonder how this "unsigned int" going to fit into this.
> Should I maybe then change it to u16 - at least that would somehow
> comply with the current declarations.
It's u16 in the struct to not waste space. In the code it's just
a number so a sized type doesn't make all that much sense.
And I think most of the code uses int/unsigned int for it anyway.
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-03-10 20:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 16:11 [Intel-gfx] [PATCH v19 0/8] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 1/8] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-10 14:32 ` Ville Syrjälä
2020-03-10 14:54 ` Lisovskiy, Stanislav
2020-03-10 20:44 ` Ville Syrjälä [this message]
2020-03-11 9:16 ` Stanislav Lisovskiy
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 2/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
[not found] ` <20200311160727.GA13686@intel.com>
2020-03-13 8:42 ` Lisovskiy, Stanislav
2020-03-09 16:11 ` [Intel-gfx] [PATCH v19 3/8] drm/i915: Add intel_bw_get_*_state helpers Stanislav Lisovskiy
[not found] ` <20200311160854.GB13686@intel.com>
2020-03-13 8:49 ` Lisovskiy, Stanislav
2020-03-13 13:26 ` Ville Syrjälä
2020-03-13 13:57 ` Lisovskiy, Stanislav
2020-03-13 14:14 ` Ville Syrjälä
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 4/8] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2020-03-11 9:13 ` Stanislav Lisovskiy
[not found] ` <20200311163130.GC13686@intel.com>
2020-03-18 11:52 ` Lisovskiy, Stanislav
2020-03-18 12:50 ` Ville Syrjälä
2020-03-19 13:09 ` Lisovskiy, Stanislav
2020-03-20 12:51 ` Lisovskiy, Stanislav
2020-03-23 14:18 ` Ville Syrjälä
2020-03-23 14:36 ` Lisovskiy, Stanislav
2020-03-23 14:50 ` Ville Syrjälä
2020-03-23 14:58 ` Lisovskiy, Stanislav
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-03-09 16:12 ` [Intel-gfx] [PATCH v19 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-03-09 16:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support Patchwork
2020-03-10 13:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-11 12:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor Gen11+ SAGV support (rev3) Patchwork
2020-03-11 14:20 ` Lisovskiy, Stanislav
2020-03-11 19:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev4) Patchwork
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