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From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/dp: Register definition for DP compliance register
Date: Fri, 27 Mar 2020 11:45:04 -0700	[thread overview]
Message-ID: <20200327184503.GB22190@intel.com> (raw)
In-Reply-To: <20200324051111.29398-1-animesh.manna@intel.com>

On Tue, Mar 24, 2020 at 10:41:11AM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
> 
> v1: Initial patch.
> v2: used pipe instead of port in macro definition. [Manasi]
> v3: used trans_offset for offset calculation. [Manasi]
> v4: Used MMIO_PIPE for evenly spaced register offset instead
> MMIO_PIPE2. [Ville]
> 
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 309cb7d96b35..465862ed2cf8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9792,6 +9792,24 @@ enum skl_power_gate {
>  #define  DDI_BUF_BALANCE_LEG_ENABLE	(1 << 31)
>  #define DDI_BUF_TRANS_HI(port, i)	_MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>  
> +/* DDI DP Compliance Control */
> +#define _DDI_DP_COMP_CTL_A			0x605F0
> +#define _DDI_DP_COMP_CTL_B			0x615F0
> +#define DDI_DP_COMP_CTL(pipe)			_MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)

This looks good now.

> +#define   DDI_DP_COMP_CTL_ENABLE		(1 << 31)
> +#define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
> +#define   DDI_DP_COMP_CTL_SCRAMBLED_0		(1 << 28)
> +#define   DDI_DP_COMP_CTL_PRBS7			(2 << 28)
> +#define   DDI_DP_COMP_CTL_CUSTOM80		(3 << 28)
> +#define   DDI_DP_COMP_CTL_HBR2			(4 << 28)
> +#define   DDI_DP_COMP_CTL_SCRAMBLED_1		(5 << 28)
> +#define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define _DDI_DP_COMP_PAT_A			0x605F4
> +#define _DDI_DP_COMP_PAT_B			0x615F4
> +#define DDI_DP_COMP_PAT(pipe, i)		_MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)

I still dont understand why we need to use that i argument here and why cant just pipe give us the desired offset
with _MMIO_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) ?

IMO we should be able to use the above since even here the registers are evenly offseted (0x605F4, 0x615F4, 0x62F54, 0x63F54)

Regards
Manasi

> +
>  /* Sideband Interface (SBI) is programmed indirectly, via
>   * SBI_ADDR, which contains the register offset; and SBI_DATA,
>   * which contains the payload */
> -- 
> 2.24.0
> 
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  reply	other threads:[~2020-03-27 18:43 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 10:37 [Intel-gfx] [PATCH v5 0/7] DP Phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 1/7] drm/amd/display: Align macro name as per DP spec Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 2/7] drm/dp: get/set phy compliance pattern Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 3/7] drm/i915/dp: Made intel_dp_adjust_train() non-static Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 4/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 5/7] drm/i915/dp: Add debugfs entry for DP phy compliance Animesh Manna
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 6/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2020-03-17  0:13   ` Manasi Navare
2020-03-18  6:35     ` [Intel-gfx] [PATCH v6 " Animesh Manna
2020-03-18 20:04       ` Manasi Navare
2020-03-19  6:39         ` Manna, Animesh
2020-03-19 16:02           ` Ville Syrjälä
2020-03-19 21:51             ` Manasi Navare
2020-03-24  5:11               ` [Intel-gfx] [PATCH v7 " Animesh Manna
2020-03-27 18:45                 ` Manasi Navare [this message]
2020-03-30  4:01                   ` Manna, Animesh
2020-03-31  0:22                     ` Manasi Navare
2020-03-16 10:37 ` [Intel-gfx] [PATCH v5 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2020-04-06 15:09   ` Manasi Navare
2020-03-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev7) Patchwork
2020-03-17  3:48 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-03-18  8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success for DP Phy compliance auto test (rev8) Patchwork
2020-03-18 10:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-24  5:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DP Phy compliance auto test (rev9) Patchwork
2020-03-24  6:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-24  7:47 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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