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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR
Date: Tue, 31 Mar 2020 18:37:26 +0300	[thread overview]
Message-ID: <20200331153726.GQ13686@intel.com> (raw)
In-Reply-To: <20200330210044.130510-2-jose.souza@intel.com>

On Mon, Mar 30, 2020 at 02:00:43PM -0700, José Roberto de Souza wrote:
> EHL has now only one table for all DP rates.
> 
> BSpec: 21257
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

1-2 are
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 053b21c11b0c..dedb86712a98 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -568,7 +568,7 @@ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
>  	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
>  };
>  
> -static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = {
> +static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  						/* NT mV Trans mV db    */
>  	{ 0xA, 0x33, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
>  	{ 0xA, 0x47, 0x36, 0x00, 0x09 },	/* 350   500      3.1   */
> @@ -947,10 +947,9 @@ static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
>  			int *n_entries)
>  {
> -	if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP &&
> -	    rate > 270000) {
> -		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3);
> -		return ehl_combo_phy_ddi_translations_hbr2_hbr3;
> +	if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) {
> +		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
> +		return ehl_combo_phy_ddi_translations_dp;
>  	}
>  
>  	return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);
> -- 
> 2.26.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-03-31 15:37 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-30 21:00 [Intel-gfx] [PATCH v2 1/3] drm/i915/dp: Return the right vswing tables José Roberto de Souza
2020-03-30 21:00 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/dp/ehl: Update vswing table for HBR and RBR José Roberto de Souza
2020-03-31 15:37   ` Ville Syrjälä [this message]
2020-03-30 21:00 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/tc/icl: Update TC vswing tables José Roberto de Souza
2020-03-31 20:20   ` Taylor, Clinton A
2020-03-31  1:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/dp: Return the right " Patchwork
2020-03-31 10:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-31 20:48   ` Souza, Jose
2020-03-31 23:52 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/3] drm/i915/dp: Return the right vswing tables (rev2) Patchwork

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