From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Move the TRANS_DDI_FUNC_CTL enable to a later point
Date: Mon, 20 Apr 2020 21:27:20 +0300 [thread overview]
Message-ID: <20200420182720.GZ6112@intel.com> (raw)
In-Reply-To: <87mu761aj6.fsf@intel.com>
On Mon, Apr 20, 2020 at 05:45:01PM +0300, Jani Nikula wrote:
> On Fri, 17 Apr 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > No reason that I can see why we should enable TRANS_DDI_FUNC_CTL
> > before we set up the watermarks of confogiure the mbus stuff.
> > In fact reordering these seems to match the bspec sequence better,
> > and cricually will allow us to push the TRANS_DDI_FUNC_CTL enable
> ^^^^^^^^^
>
> The entire series is nice, but I especially like this "crucially"
> typo. It looks prezactly like a mix of crucially and critically.
Wasn't the only typo. One day I need to invest in a spell checker.
>
> FWIW the series is Acked-by me, as Chris beat me to review. I also
> didn't spot anything obviously wrong.
Thanks for the reviews/acks. Series pushed to dinq.
>
> BR,
> Jani.
>
>
> > into the encoder enable hook as a followup.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index af5b4055b38a..7a1e7b5ae84e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7071,15 +7071,15 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_set_pipe_chicken(crtc);
> >
> > - if (!transcoder_is_dsi(cpu_transcoder))
> > - intel_ddi_enable_transcoder_func(new_crtc_state);
> > -
> > if (dev_priv->display.initial_watermarks)
> > dev_priv->display.initial_watermarks(state, crtc);
> >
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_pipe_mbus_enable(crtc);
> >
> > + if (!transcoder_is_dsi(cpu_transcoder))
> > + intel_ddi_enable_transcoder_func(new_crtc_state);
> > +
> > intel_encoders_enable(state, crtc);
> >
> > if (psl_clkgate_wa) {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-04-20 18:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-17 13:47 [Intel-gfx] [PATCH 1/4] drm/i195: Pass encoder to intel_ddi_enable_pipe_clock() Ville Syrjala
2020-04-17 13:47 ` [Intel-gfx] [PATCH 2/4] drm/i915: Move the TRANS_DDI_FUNC_CTL enable to a later point Ville Syrjala
2020-04-17 19:53 ` Chris Wilson
2020-04-20 14:45 ` Jani Nikula
2020-04-20 18:27 ` Ville Syrjälä [this message]
2020-04-17 13:47 ` [Intel-gfx] [PATCH 3/4] drm/i915: Push TRANS_DDI_FUNC_CTL into the encoder->enable() hook Ville Syrjala
2020-04-17 19:51 ` Chris Wilson
2020-04-20 18:34 ` Ville Syrjälä
2020-04-17 13:47 ` [Intel-gfx] [PATCH 4/4] drm/i915: Pass encoder all the way to intel_ddi_transcoder_func_reg_val_get() Ville Syrjala
2020-04-17 19:45 ` Chris Wilson
2020-04-17 19:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/4] drm/i195: Pass encoder to intel_ddi_enable_pipe_clock() Patchwork
2020-04-17 19:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-17 19:52 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson
2020-04-19 6:06 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork
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