From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 01/11] HAX to make DSC work on the icelake test system
Date: Thu, 30 Apr 2020 16:09:41 -0700 [thread overview]
Message-ID: <20200430230951.2508-2-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20200430230951.2508-1-manasi.d.navare@intel.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
DSC is available on the display emulator, but not set in DPCD.
Override the entries to allow bigjoiner testing.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 612a59ec8116..475e99990086 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1425,7 +1425,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
} else {
@@ -1449,7 +1449,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6c4b53dcb851..cf2ee635270c 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1413,6 +1413,7 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SI
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
{
+ return dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT];
return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
DP_DSC_DECOMPRESSION_IS_SUPPORTED;
}
--
2.19.1
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next prev parent reply other threads:[~2020-04-30 23:08 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 23:09 [Intel-gfx] [PATCH v4 00/11] Rebased Big Joiner patch series for 8K 2p1p Manasi Navare
2020-04-30 23:09 ` Manasi Navare [this message]
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 02/11] drm/i915: Remove hw.mode Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 03/11] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split Manasi Navare
2020-05-01 5:18 ` [Intel-gfx] [PATCH v5 " Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 04/11] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3 Manasi Navare
2020-05-06 13:35 ` Maarten Lankhorst
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 05/11] drm/i915: Try to make bigjoiner work in atomic check Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 06/11] drm/i915: Enable big joiner support in enable and disable sequences Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 07/11] drm/i915: Make hardware readout work on i915 Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 08/11] drm/i915: Link planes in a bigjoiner configuration, v3 Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 09/11] drm/i915: Add bigjoiner aware plane clipping checks Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 10/11] drm/i915: Add intel_update_bigjoiner handling Manasi Navare
2020-04-30 23:09 ` [Intel-gfx] [PATCH v4 11/11] drm/i915: Add debugfs dumping for bigjoiner, v3 Manasi Navare
2020-04-30 23:57 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Rebased Big Joiner patch series for 8K 2p1p Patchwork
2020-05-01 5:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rebased Big Joiner patch series for 8K 2p1p (rev2) Patchwork
2020-05-01 5:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-01 9:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 14:45 ` [Intel-gfx] [PATCH v4 00/11] Rebased Big Joiner patch series for 8K 2p1p Maarten Lankhorst
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