Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value when disabling TRANS_DDI

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, May 13, 2020 at 03:09:52PM +0300, Ville Syrjälä wrote:
> On Wed, May 13, 2020 at 01:58:47PM +0530, Sharma, Swati2 wrote:
> > 
> > 
> > On 31-Jan-20 4:50 PM, Ville Syrjälä wrote:
> > > On Thu, Jan 30, 2020 at 08:07:07PM +0000, Souza, Jose wrote:
> > >> On Thu, 2020-01-30 at 19:25 +0200, Ville Syrjälä wrote:
> > >>> On Thu, Jan 16, 2020 at 05:58:37PM -0800, José Roberto de Souza
> > >>> wrote:
> > >>>> TGL timeouts when disabling MST transcoder and fifo underruns over
> > >>>> MST
> > >>>> transcoders are fixed when setting TRANS_DDI_MODE_SELECT to 0(HDMI
> > >>>> mode) during the disable sequence.
> > >>>>
> > >>>> Although BSpec disable sequence don't require this step it is a
> > >>>> harmless change and it is also done by Windows driver.
> > >>>> Anyhow HW team was notified about that but it can take some time to
> > >>>> documentation to be updated.
> > >>>>
> > >>>> A case that always lead to those issues is:
> > >>>> - do a modeset enabling pipe A and pipe B in the same MST stream
> > >>>> leaving A as master
> > >>>> - disable pipe A, promote B as master doing a full modeset in A
> > >>>> - enable pipe A, changing the master transcoder back to A(doing a
> > >>>> full modeset in B)
> > >>>> - Pow: underruns and timeouts
> > >>>>
> > >>>> The transcoders involved will only work again when complete
> > >>>> disabled
> > >>>> and their power wells turned off causing a reset in their
> > >>>> registers.
> > >>>>
> > >>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>>> Cc: Matt Roper <matthew.d.roper@intel.com>
> > >>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > >>>> ---
> > >>>>   drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> > >>>>   1 file changed, 1 insertion(+)
> > >>>>
> > >>>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >>>> b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >>>> index 32ea3c7e8b62..82e90f271974 100644
> > >>>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > >>>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > >>>> @@ -1997,6 +1997,7 @@ void intel_ddi_disable_transcoder_func(const
> > >>>> struct intel_crtc_state *crtc_state
> > >>>>   
> > >>>>   	val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > >>>>   	val &= ~TRANS_DDI_FUNC_ENABLE;
> > >>>> +	val &= ~TRANS_DDI_MODE_SELECT_MASK;
> > >>>
> > >>> Feels a bit early since IIRC we still leave a bunch of other stuff
> > >>> enabled/selected here. In fact we don't seem to be clearing the DDI
> > >>> select
> > >>> anywhere at all? That one I would be more suspicious of than the
> > >>> mode.
> > >>> But maybe we should just clear both somewhere? I would suggest it
> > >>> should
> > >>> be when we clear the port select finally.
> > >>
> > >> We are clearing DDI select, in our code it is named as
> > >> TGL_TRANS_DDI_PORT_MASK/TRANS_DDI_PORT_MASK.
> > >>
> > >> For TGL in MST mode we clear DDI select in the block below for MST
> > >> slaves and then in intel_ddi_post_disable_dp() for MST master as
> > >> instructed by Display port sequences.
> > > 
> > > Ah. Hmm, so that can't be it then. Bummer. I guess I would still feel
> > > a bit safer if we clear the mode select alongside the the DDI select
> > > for the master. Since the spec says the DDI select must remain set for
> > > the master there must be something still going on, and so I worry that
> > > something might not work quite right if we change the mode
> > > prematurely.
> > 
> > Hi Ville/Jose,
> > 
> > We are still observing
> > =>*ERROR* Timed out waiting for ACT sent when disabling
> > =>FIFO underruns
> > Do we need a change disable sequence?
> 
> My crystal ball is foggy today. If you want to know whether there is a
> mismatch between the spec and code you're just going to have to read
> both and compare.

If if there is no difference then it may become a fun task of trial and
error to see what about the current order the hardware doesn't like.

-- 
Ville Syrjälä
Intel
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