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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [Intel-gfx] [v5 06/11] drm/i915/display: Implement infoframes readback for LSPCON
Date: Tue, 23 Jun 2020 01:30:33 +0530	[thread overview]
Message-ID: <20200622200038.14034-7-uma.shankar@intel.com> (raw)
In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com>

Implemented Infoframes enabled readback for LSPCON devices.
This will help align the implementation with state readback
infrastructure.

v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++-
 1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 9034ce6f20b9..0f19eb6c5a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 				  buf, ret);
 }
 
+static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
+{
+	int ret;
+	u32 val = 0;
+	u16 reg = LSPCON_MCA_AVI_IF_CTRL;
+
+	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
+	if (ret < 0) {
+		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+		return false;
+	}
+
+	return val & LSPCON_MCA_AVI_IF_KICKOFF;
+}
+
+static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
+{
+	int ret;
+	u32 val = 0;
+	u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
+
+	ret = drm_dp_dpcd_read(aux, reg, &val, 1);
+	if (ret < 0) {
+		DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
+		return false;
+	}
+
+	return val & LSPCON_PARADE_AVI_IF_KICKOFF;
+}
+
 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
 {
-	/* FIXME actually read this from the hw */
-	return 0;
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	bool infoframes_enabled;
+	u32 val = 0;
+	u32 mask, tmp;
+
+	if (lspcon->vendor == LSPCON_VENDOR_MCA)
+		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
+	else
+		infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
+
+	if (infoframes_enabled)
+		val |= VIDEO_DIP_ENABLE_AVI_HSW;
+
+	if (lspcon->hdr_supported) {
+		tmp = intel_de_read(dev_priv,
+				    HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
+		mask = VIDEO_DIP_ENABLE_GMP_HSW;
+
+		if (tmp & mask)
+			val |= mask;
+	}
+
+	return val;
 }
 
 void lspcon_resume(struct intel_lspcon *lspcon)
-- 
2.22.0

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  parent reply	other threads:[~2020-06-22 19:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-22 20:00 [Intel-gfx] [v5 00/11] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-06-22 19:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev5) Patchwork
2020-06-22 20:00 ` [Intel-gfx] [v5 01/11] drm/i915/display: Add HDR Capability detection for LSPCON Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 05/11] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-06-22 20:00 ` Uma Shankar [this message]
2020-06-22 20:00 ` [Intel-gfx] [v5 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 10/11] drm/i915/lspcon: Do not send DRM " Uma Shankar
2020-06-22 20:00 ` [Intel-gfx] [v5 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-06-22 20:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable HDR on MCA LSPCON based Gen9 devices (rev5) Patchwork
2020-06-22 21:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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