From: Manasi Navare <manasi.d.navare@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print
Date: Thu, 2 Jul 2020 12:27:42 -0700 [thread overview]
Message-ID: <20200702192741.GA32432@intel.com> (raw)
In-Reply-To: <20200702182450.6804-2-ville.syrjala@linux.intel.com>
On Thu, Jul 02, 2020 at 09:24:50PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we claim to use TPS7 when using TPS4. That is just
> confusing, so let's fix the debug print.
>
> And while we're touching this let's add the customary
> encoder id/name as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++-----
> 1 file changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5ac182357fc9..eba97b1f5839 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4353,17 +4353,33 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> intel_dp->set_signal_levels(intel_dp);
> }
>
> +static char dp_training_pattern_name(u8 train_pat)
> +{
> + switch (train_pat) {
> + case DP_TRAINING_PATTERN_1:
> + case DP_TRAINING_PATTERN_2:
> + case DP_TRAINING_PATTERN_3:
> + return '0' + train_pat;
> + case DP_TRAINING_PATTERN_4:
> + return '4';
> + default:
> + return '?';
Shouldnt this be a WARN? If we just return a ? it might result into failure without any warn
Other than that I like that now it will say TPS4 instead of misleading TPS7
So with a default WARN,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> + }
> +}
> +
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> {
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + u8 train_pat = dp_train_pat & drm_dp_training_pattern_mask(intel_dp->dpcd);
>
> - if (dp_train_pat & train_pat_mask)
> + if (train_pat)
> drm_dbg_kms(&dev_priv->drm,
> - "Using DP training pattern TPS%d\n",
> - dp_train_pat & train_pat_mask);
> + "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
> + encoder->base.base.id, encoder->base.name,
> + dp_training_pattern_name(train_pat));
>
> intel_dp->set_link_train(intel_dp, dp_train_pat);
> }
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-07-02 19:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 18:24 [Intel-gfx] [PATCH 1/2] drm/i915: Enable TPS3/4 on all platforms that support them Ville Syrjala
2020-07-02 18:24 ` [Intel-gfx] [PATCH 2/2] drm/i915: Fix the training pattern debug print Ville Syrjala
2020-07-02 19:27 ` Manasi Navare [this message]
2020-07-03 10:56 ` Ville Syrjälä
2020-07-02 19:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Enable TPS3/4 on all platforms that support them Patchwork
2020-07-02 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-02 22:38 ` [Intel-gfx] [PATCH 1/2] " Manasi Navare
2020-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
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