From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris.p.wilson@intel.com>
Subject: [Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers
Date: Wed, 29 Jul 2020 17:48:25 -0700 [thread overview]
Message-ID: <20200730004826.8415-6-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com>
From: Piotr Maciejewski <piotr.maciejewski@intel.com>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
v2:
- Bump up the perf revision (Lionel)
- Use indexing for counters (Lionel)
- Fix selftest for oa ticking register (Umesh)
v3: Pardon whitelisted registers for selftest (Umesh)
v4:
- Document whitelisted registers (Lionel)
- Fix live isolated whitelist for OA regs (Umesh)
v5:
- Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_perf.c | 10 +++++++++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e096282ad547..f4bd15d6b75f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1677,9 +1677,17 @@ struct i915_oa_wl {
} gen9_oa_regs[] = {
{ OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
}, gen12_oa_regs[] = {
{ GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW },
{ GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW },
+ { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
+ { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4 },
};
static void whitelist_delete_perf_counters(struct i915_wa_list *wal,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0e2313d50c91..9b55521cb09b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4472,8 +4472,16 @@ int i915_perf_ioctl_version(void)
* into the OA buffer. This applies only to gen8+. The feature can
* only be accessed if perf_stream_paranoid is set to 0 by privileged
* user.
+ *
+ * 7: Whitelist below OA registers for user to identify the location of
+ * triggered reports in the OA buffer. This applies only to gen8+.
+ * The feature can only be accessed if perf_stream_paranoid is set to
+ * 0 by privileged user.
+ *
+ * - OA buffer head/tail/status/buffer registers for read only
+ * - OA counters A18, A19, A20 for read/write
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cc3e312b6b7..6b30f076d8eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4)
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx))
+#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
--
2.20.1
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next prev parent reply other threads:[~2020-07-30 0:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-30 0:48 [Intel-gfx] [PATCH 0/6] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-07-30 0:48 ` [Intel-gfx] [PATCH 1/6] drm/i915: Allow removal of whitelist register and refactor Umesh Nerlige Ramappa
2020-07-30 0:48 ` [Intel-gfx] [PATCH 2/6] drm/i915/selftests: Clear flags when using wa->reg for comparison Umesh Nerlige Ramappa
2020-07-30 0:48 ` [Intel-gfx] [PATCH 3/6] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
2020-07-30 0:48 ` [Intel-gfx] [PATCH 4/6] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-07-30 8:14 ` Chris Wilson
2020-07-30 0:48 ` Umesh Nerlige Ramappa [this message]
2020-07-30 0:48 ` [Intel-gfx] [PATCH 6/6] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
2020-07-30 9:00 ` Chris Wilson
2020-07-30 9:08 ` Chris Wilson
2020-07-30 1:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Allow privileged user to map the OA buffer (rev6) Patchwork
2020-07-30 1:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-30 1:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-30 2:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-10-02 23:27 [Intel-gfx] [PATCH 0/6] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-10-02 23:28 ` [Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-10-10 0:20 [Intel-gfx] [PATCH 0/6] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-10-10 0:21 ` [Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
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