From: Ramalingam C <ramalingam.c@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: No direct access to power_well desc
Date: Wed, 5 Aug 2020 19:02:29 +0530 [thread overview]
Message-ID: <20200805133229.GB8131@intel.com> (raw)
In-Reply-To: <20200805114521.867-3-anshuman.gupta@intel.com>
On 2020-08-05 at 17:15:21 +0530, Anshuman Gupta wrote:
> HDCP code doesn't require to access power_well internal stuff,
> instead it should use the intel_display_power_well_is_enabled()
> to get the status of desired power_well.
> No functional change.
>
> v2:
> - used with_intel_runtime_pm instead of get/put. [Jani]
> v3:
> - rebased.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
LGTM.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
-Ram
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++------------
> 1 file changed, 3 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index a1e0d518e529..e76b049618db 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -148,9 +148,8 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port,
>
> static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
> {
> - struct i915_power_domains *power_domains = &dev_priv->power_domains;
> - struct i915_power_well *power_well;
> enum i915_power_well_id id;
> + intel_wakeref_t wakeref;
> bool enabled = false;
>
> /*
> @@ -162,17 +161,9 @@ static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
> else
> id = SKL_DISP_PW_1;
>
> - mutex_lock(&power_domains->lock);
> -
> /* PG1 (power well #1) needs to be enabled */
> - for_each_power_well(dev_priv, power_well) {
> - if (power_well->desc->id == id) {
> - enabled = power_well->desc->ops->is_enabled(dev_priv,
> - power_well);
> - break;
> - }
> - }
> - mutex_unlock(&power_domains->lock);
> + with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
> + enabled = intel_display_power_well_is_enabled(dev_priv, id);
>
> /*
> * Another req for hdcp key loadability is enabled state of pll for
> --
> 2.26.2
>
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next prev parent reply other threads:[~2020-08-05 13:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-05 11:45 [Intel-gfx] [PATCH v3 0/2] HDCP minor refactoring Anshuman Gupta
2020-08-05 11:45 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/hdcp: Add update_pipe early return Anshuman Gupta
2020-08-05 13:16 ` Ramalingam C
2020-08-05 11:45 ` [Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: No direct access to power_well desc Anshuman Gupta
2020-08-05 13:32 ` Ramalingam C [this message]
2020-08-05 12:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for HDCP minor refactoring (rev3) Patchwork
2020-08-05 16:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-26 11:17 ` [Intel-gfx] [PATCH v3 0/2] HDCP minor refactoring Ramalingam C
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