From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/display/fbc: Implement WA 22010751166
Date: Mon, 19 Oct 2020 10:56:09 -0700 [thread overview]
Message-ID: <20201019175609.28715-1-jose.souza@intel.com> (raw)
Underruns happens when plane height + y offset is not a module of 4
when FBC is enabled.
Specification says that it only affects TGL display C stepping and
newer but to simply the check and as TGL is already in final costumers
hands, pre-production display stepping A and B was also included.
BSpec: 52887 ICL
BSpec: 52888 EHL/JSL
BSpec: 52890/55378 TGL
BSpec: 53508 DG1
BSpec: 53273 RKL
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 135f5e8a4d70..a5b072816a7b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -907,6 +907,13 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
+ /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
+ fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
+ return false;
+ }
+
return true;
}
--
2.28.0
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next reply other threads:[~2020-10-19 17:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-19 17:56 José Roberto de Souza [this message]
2020-10-19 18:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/fbc: Implement WA 22010751166 Patchwork
2020-10-19 20:30 ` [Intel-gfx] [PATCH] " Matt Roper
2020-10-19 21:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2020-10-20 0:33 ` Souza, Jose
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