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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris.p.wilson@intel.com>
Subject: [Intel-gfx] [PATCH 3/7] drm/i915/gt: Add a reference to the engine in i915_wa_list
Date: Fri, 13 Nov 2020 10:03:55 -0800	[thread overview]
Message-ID: <20201113180359.54410-4-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20201113180359.54410-1-umesh.nerlige.ramappa@intel.com>

Applying OA whitelist dynamically also demands that we update the wal
list in sync with engine resume. The lock currently used to synchronize
this is engine->uncore->lock. To use this lock, make i915_wa_list aware
of the engine.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c       | 12 +++++++-----
 drivers/gpu/drm/i915/gt/intel_workarounds_types.h |  1 +
 drivers/gpu/drm/i915/gt/selftest_workarounds.c    |  4 ++--
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fa8c9d86847d..0f9d2a65dcfe 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -83,10 +83,12 @@ const struct i915_rev_steppings tgl_revids[] = {
 	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
 };
 
-static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
+static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name,
+			  struct intel_engine_cs *engine)
 {
 	wal->name = name;
 	wal->engine_name = engine_name;
+	wal->engine = engine;
 }
 
 #define WA_LIST_CHUNK (1 << 4)
@@ -696,7 +698,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 	if (engine->class != RENDER_CLASS)
 		return;
 
-	wa_init_start(wal, name, engine->name);
+	wa_init_start(wal, name, engine->name, engine);
 
 	if (IS_DG1(i915))
 		dg1_ctx_workarounds_init(engine, wal);
@@ -1331,7 +1333,7 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915)
 {
 	struct i915_wa_list *wal = &i915->gt_wa_list;
 
-	wa_init_start(wal, "GT", "global");
+	wa_init_start(wal, "GT", "global", NULL);
 	gt_init_workarounds(i915, wal);
 	wa_init_finish(wal);
 }
@@ -1673,7 +1675,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 	struct drm_i915_private *i915 = engine->i915;
 	struct i915_wa_list *w = &engine->whitelist;
 
-	wa_init_start(w, "whitelist", engine->name);
+	wa_init_start(w, "whitelist", engine->name, engine);
 
 	if (IS_DG1(i915))
 		dg1_whitelist_build(engine);
@@ -2073,7 +2075,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
 	if (INTEL_GEN(engine->i915) < 4)
 		return;
 
-	wa_init_start(wal, "engine", engine->name);
+	wa_init_start(wal, "engine", engine->name, engine);
 	engine_init_workarounds(engine, wal);
 	wa_init_finish(wal);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index d166a7145720..e562fd43697b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -24,6 +24,7 @@ struct i915_wa_list {
 	struct i915_wa	*list;
 	unsigned int	count;
 	unsigned int	wa_count;
+	struct intel_engine_cs *engine;
 };
 
 #endif /* __INTEL_WORKAROUNDS_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 61a0532d0f3d..fa616d122a23 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -65,14 +65,14 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists)
 
 	memset(lists, 0, sizeof(*lists));
 
-	wa_init_start(&lists->gt_wa_list, "GT_REF", "global");
+	wa_init_start(&lists->gt_wa_list, "GT_REF", "global", NULL);
 	gt_init_workarounds(gt->i915, &lists->gt_wa_list);
 	wa_init_finish(&lists->gt_wa_list);
 
 	for_each_engine(engine, gt, id) {
 		struct i915_wa_list *wal = &lists->engine[id].wa_list;
 
-		wa_init_start(wal, "REF", engine->name);
+		wa_init_start(wal, "REF", engine->name, engine);
 		engine_init_workarounds(engine, wal);
 		wa_init_finish(wal);
 
-- 
2.20.1

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  parent reply	other threads:[~2020-11-13 18:04 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-13 18:03 [Intel-gfx] [PATCH 0/7] Allow privileged user to map the OA buffer Umesh Nerlige Ramappa
2020-11-13 18:03 ` [Intel-gfx] [PATCH 1/7] drm/i915/perf: Ensure observation logic is not clock gated Umesh Nerlige Ramappa
2020-11-13 18:03 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock Umesh Nerlige Ramappa
2020-11-13 18:03 ` Umesh Nerlige Ramappa [this message]
2020-11-13 18:03 ` [Intel-gfx] [PATCH 4/7] drm/i915/perf: Whitelist OA report trigger registers Umesh Nerlige Ramappa
2020-11-13 22:12   ` Umesh Nerlige Ramappa
2020-11-13 22:18     ` Dixit, Ashutosh
2020-11-13 18:03 ` [Intel-gfx] [PATCH 5/7] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow Umesh Nerlige Ramappa
2020-11-13 18:03 ` [Intel-gfx] [PATCH 6/7] drm/i915/perf: Whitelist OA counter and buffer registers Umesh Nerlige Ramappa
2020-11-13 18:03 ` [Intel-gfx] [PATCH 7/7] drm/i915/perf: Map OA buffer to user space for gen12 performance query Umesh Nerlige Ramappa
2020-11-13 23:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer Patchwork

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