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From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S
Date: Fri,  4 Dec 2020 17:08:29 -0800	[thread overview]
Message-ID: <20201205010844.361880-8-aditya.swarup@intel.com> (raw)
In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.

v2:
- Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
and return false for platforms RKL,DG1 and ADLS.(mdroper)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  5 ++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9187a20a8aca..2d1c5bfe4032 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
+	else if (IS_ALDERLAKE_S(dev_priv))
+		return phy <= PHY_E;
 	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_JSL_EHL(dev_priv))
@@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
-		return false;
-	else if (INTEL_GEN(dev_priv) >= 12)
+	if (IS_TIGERLAKE(dev_priv))
 		return phy >= PHY_D && phy <= PHY_I;
 	else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
@@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
+	if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+		return PHY_B + port - PORT_TC1;
+	else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
 		return PHY_C + port - PORT_TC1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cdc67f583a9c..60a0d4c35cae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
 #define _RKL_COMBOPHY_D			0x161000
+#define _ADL_COMBOPHY_E			0x16B000
+
 #define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _EHL_COMBOPHY_C, \
-					      _RKL_COMBOPHY_D)
+					      _RKL_COMBOPHY_D, \
+					      _ADL_COMBOPHY_E)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
-- 
2.27.0

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  parent reply	other threads:[~2020-12-05  1:09 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-05  1:08 [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2021-01-05 21:04   ` Souza, Jose
2020-12-05  1:08 ` [Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-12-05  1:08 ` Aditya Swarup [this message]
2021-01-12  3:33   ` [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2021-01-12  3:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2021-01-12 23:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display " Aditya Swarup
2021-01-12  3:54   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2021-01-12  4:19   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2021-01-12  4:05   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2021-01-27 14:29   ` Lucas De Marchi
2020-12-05  1:08 ` [Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-12-05  1:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev3) Patchwork
2020-12-05  1:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-12-05  1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-05  5:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-21 10:40 ` [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Jani Nikula

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