From: "Navare, Manasi" <manasi.d.navare@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT
Date: Tue, 8 Dec 2020 12:26:59 -0800 [thread overview]
Message-ID: <20201208202659.GD474@labuser-Z97X-UD5H> (raw)
In-Reply-To: <43fba75d89525413aed0bdbb082c26b09458bd46.1607429866.git.jani.nikula@intel.com>
On Tue, Dec 08, 2020 at 02:33:54PM +0200, Jani Nikula wrote:
> The VBT fields match the DPCD data, so use the same helper.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Only for DSI so far right?
In that case looks good
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..06c3310446a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2555,16 +2555,11 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
> crtc_state->dsc.slice_count);
>
> /*
> - * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
> - * implementation specific physical rate buffer size. Currently we use
> - * the required rate buffer model size calculated in
> - * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
> - *
> * The VBT rc_buffer_block_size and rc_buffer_size definitions
> - * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
> - * implementation should also use the DPCD (or perhaps VBT for eDP)
> - * provided value for the buffer size.
> + * correspond to DP 1.4 DPCD offsets 0x62 and 0x63.
> */
> + vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size,
> + dsc->rc_buffer_size);
>
> /* FIXME: DSI spec says bpc + 1 for this one */
> vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
> --
> 2.20.1
>
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next prev parent reply other threads:[~2020-12-08 20:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-08 12:33 [Intel-gfx] [PATCH 0/6] drm/dsc, drm/dp, and /drm/i915: rc model size updates Jani Nikula
2020-12-08 12:33 ` [Intel-gfx] [PATCH 1/6] drm/dsc: use rc_model_size from DSC config for PPS Jani Nikula
2020-12-08 12:33 ` [Intel-gfx] [PATCH 2/6] drm/i915/dsc: configure hardware using specified rc_model_size Jani Nikula
2020-12-08 12:33 ` [Intel-gfx] [PATCH 3/6] drm/i915/dsc: make rc_model_size an encoder defined value Jani Nikula
2020-12-08 20:24 ` Navare, Manasi
2020-12-08 12:33 ` [Intel-gfx] [PATCH 4/6] drm/dsc: add helper for calculating rc buffer size from DPCD Jani Nikula
2020-12-08 12:33 ` [Intel-gfx] [PATCH 5/6] drm/i915/bios: fill in DSC rc_model_size from VBT Jani Nikula
2020-12-08 20:26 ` Navare, Manasi [this message]
2020-12-10 9:53 ` Jani Nikula
2020-12-08 12:33 ` [Intel-gfx] [PATCH 6/6] drm/i915/dsi: use VBT data for rc_model_size Jani Nikula
2020-12-08 16:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dsc, drm/dp, and /drm/i915: rc model size updates Patchwork
2020-12-08 16:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-12-08 17:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-08 21:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-12-09 9:34 ` [Intel-gfx] [PATCH 0/6] " Jani Nikula
2020-12-09 19:41 ` Daniel Vetter
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