From: Ramalingam C <ramalingam.c@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, seanpaul@chromium.org
Subject: Re: [Intel-gfx] [PATCH v8 17/19] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Date: Mon, 14 Dec 2020 19:02:34 +0530 [thread overview]
Message-ID: <20201214133234.GB22687@intel.com> (raw)
In-Reply-To: <20201211134244.14588-18-anshuman.gupta@intel.com>
On 2020-12-11 at 19:12:42 +0530, Anshuman Gupta wrote:
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication
> and Encryption and HDCP 2.2 stream encryption
> callback.
>
> v2:
> - Added a WARN_ON() instead of drm_err. [Uma]
> - Cosmetic changes. [Uma]
> v3:
> - 's/port_data/hdcp_port_data' [Ram]
> - skip redundant link check. [Ram]
> v4:
> - use pipe instead of port to access HDCP2_STREAM_STATUS
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> Tested-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 89 +++++++++++++++++--
> 2 files changed, 85 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 63de25b40eff..da91e3f4ff27 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -378,6 +378,10 @@ struct intel_hdcp_shim {
> int (*config_stream_type)(struct intel_digital_port *dig_port,
> bool is_repeater, u8 type);
>
> + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> + int (*stream_2_2_encryption)(struct intel_connector *connector,
> + bool enable);
> +
> /* HDCP2.2 Link Integrity Check */
> int (*check_2_2_link)(struct intel_digital_port *dig_port,
> struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 9ade1ad3a80c..f372e25edab4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
> return 0;
> }
>
> -static
> -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> - struct intel_connector *connector)
> +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *intel_dp = &dig_port->dp;
> struct drm_dp_query_stream_enc_status_ack_reply reply;
> + struct intel_dp *intel_dp = &dig_port->dp;
> int ret;
>
> - if (!intel_dp_hdcp_check_link(dig_port, connector))
> - return false;
> -
> ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> connector->port, &reply);
> if (ret) {
> @@ -726,6 +722,78 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> return reply.auth_completed && reply.encryption_enabled;
> }
>
> +static
> +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> +{
> + if (!intel_dp_hdcp_check_link(dig_port, connector))
> + return false;
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector);
> +}
> +
> +static int
> +intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
> + bool enable)
> +{
> + struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> + struct intel_hdcp *hdcp = &connector->hdcp;
> + enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> + enum pipe pipe = (enum pipe)cpu_transcoder;
> + enum port port = dig_port->base.port;
> + int ret;
> +
> + drm_WARN_ON(&i915->drm, enable &&
> + !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> + & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
> +
> + ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
> + if (ret)
> + return ret;
> +
> + /* Wait for encryption confirmation */
> + if (intel_de_wait_for_register(i915,
> + HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
> + STREAM_ENCRYPTION_STATUS,
> + enable ? STREAM_ENCRYPTION_STATUS : 0,
> + HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> + drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
> + transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
> + * I.3.5 MST source device may use a QSES msg to query downstream status
> + * for a particular stream.
> + */
> +static
> +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
> + struct intel_connector *connector)
> +{
> + struct intel_hdcp *hdcp = &connector->hdcp;
> + int ret;
> +
> + /*
> + * We do need to do the Link Check only for the connector involved with
> + * HDCP port authentication and encryption.
> + * We can re-use the hdcp->is_repeater flag to know that the connector
> + * involved with HDCP port authentication and encryption.
> + */
> + if (hdcp->is_repeater) {
> + ret = intel_dp_hdcp2_check_link(dig_port, connector);
> + if (ret)
> + return ret;
> + }
> +
> + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
> +}
> +
> static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .write_an_aksv = intel_dp_hdcp_write_an_aksv,
> .read_bksv = intel_dp_hdcp_read_bksv,
> @@ -739,7 +807,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
> .check_link = intel_dp_mst_hdcp_check_link,
> .hdcp_capable = intel_dp_hdcp_capable,
> -
> + .write_2_2_msg = intel_dp_hdcp2_write_msg,
> + .read_2_2_msg = intel_dp_hdcp2_read_msg,
> + .config_stream_type = intel_dp_hdcp2_config_stream_type,
> + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
> + .check_2_2_link = intel_dp_mst_hdcp2_check_link,
> + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
> .protocol = HDCP_PROTOCOL_DP,
> };
>
> --
> 2.26.2
>
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next prev parent reply other threads:[~2020-12-14 13:32 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 13:42 [Intel-gfx] [PATCH v8 00/19] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 01/19] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 02/19] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 03/19] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 04/19] drm/i915/hdcp: No HDCP when encoder is't initialized Anshuman Gupta
2020-12-14 14:10 ` Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 05/19] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 06/19] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 07/19] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 09/19] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 10/19] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 11/19] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 13/19] drm/hdcp: Max MST content streams Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 14/19] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 15/19] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 16/19] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 17/19] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2020-12-14 13:32 ` Ramalingam C [this message]
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 18/19] drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status Anshuman Gupta
2020-12-14 13:35 ` Ramalingam C
2020-12-11 13:42 ` [Intel-gfx] [PATCH v8 19/19] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2020-12-14 13:25 ` Ramalingam C
2020-12-11 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev7) Patchwork
2020-12-11 15:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-12-14 15:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev8) Patchwork
2020-12-14 15:37 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
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