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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: jani.nikula@intel.com, seanpaul@chromium.org
Subject: [Intel-gfx] [PATCH v9 16/19] drm/i915/hdcp: Add HDCP 2.2 stream register
Date: Mon, 11 Jan 2021 13:41:17 +0530	[thread overview]
Message-ID: <20210111081120.28417-17-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20210111081120.28417-1-anshuman.gupta@intel.com>

Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.

B.Spec: 21780
B.Spec: 14410
B.Spec: 50573

v2
- Modified naming convention of HDCP2_STREAM_STATUS
  for pre-gen12 platforms inline with B.Spec.

Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Tested-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 39 +++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b448e507d41e..cade0a7a97b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9873,6 +9873,7 @@ enum skl_power_gate {
 					  _PORTD_HDCP2_BASE, \
 					  _PORTE_HDCP2_BASE, \
 					  _PORTF_HDCP2_BASE) + (x))
+
 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
 #define _TRANSA_HDCP2_AUTH		0x66498
 #define _TRANSB_HDCP2_AUTH		0x66598
@@ -9912,6 +9913,44 @@ enum skl_power_gate {
 					 TRANS_HDCP2_STATUS(trans) : \
 					 PORT_HDCP2_STATUS(port))
 
+#define _PIPEA_HDCP2_STREAM_STATUS	0x668C0
+#define _PIPEB_HDCP2_STREAM_STATUS	0x665C0
+#define _PIPEC_HDCP2_STREAM_STATUS	0x666C0
+#define _PIPED_HDCP2_STREAM_STATUS	0x667C0
+#define PIPE_HDCP2_STREAM_STATUS(pipe)		_MMIO(_PICK((pipe), \
+						      _PIPEA_HDCP2_STREAM_STATUS, \
+						      _PIPEB_HDCP2_STREAM_STATUS, \
+						      _PIPEC_HDCP2_STREAM_STATUS, \
+						      _PIPED_HDCP2_STREAM_STATUS))
+
+#define _TRANSA_HDCP2_STREAM_STATUS		0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS		0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_STREAM_STATUS, \
+						    _TRANSB_HDCP2_STREAM_STATUS)
+#define   STREAM_ENCRYPTION_STATUS	BIT(31)
+#define   STREAM_TYPE_STATUS		BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_STREAM_STATUS(trans) : \
+					 PIPE_HDCP2_STREAM_STATUS(pipe))
+
+#define _PORTA_HDCP2_AUTH_STREAM		0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM		0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \
+						   _PORTA_HDCP2_AUTH_STREAM, \
+						   _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM		0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM		0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \
+						    _TRANSA_HDCP2_AUTH_STREAM, \
+						    _TRANSB_HDCP2_AUTH_STREAM)
+#define   AUTH_STREAM_TYPE		BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+					(INTEL_GEN(dev_priv) >= 12 ? \
+					 TRANS_HDCP2_AUTH_STREAM(trans) : \
+					 PORT_HDCP2_AUTH_STREAM(port))
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A		0x60400
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
-- 
2.26.2

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  parent reply	other threads:[~2021-01-11  8:27 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-11  8:11 [Intel-gfx] [PATCH v9 00/19] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 01/19] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 02/19] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 03/19] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 04/19] drm/i915/hdcp: No HDCP when encoder is't initialized Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 05/19] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 06/19] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 07/19] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 09/19] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 10/19] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 11/19] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 13/19] drm/hdcp: Max MST content streams Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 14/19] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta
2021-01-12  5:26   ` Li, Juston
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 15/19] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2021-01-11  8:11 ` Anshuman Gupta [this message]
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 17/19] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 18/19] drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status Anshuman Gupta
2021-01-11  8:11 ` [Intel-gfx] [PATCH v9 19/19] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2021-01-11  8:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev9) Patchwork
2021-01-13  3:40   ` Gupta, Anshuman

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