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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 02/11] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
Date: Mon, 11 Jan 2021 12:35:45 -0500	[thread overview]
Message-ID: <20210111173545.GB3689@intel.com> (raw)
In-Reply-To: <20210110150404.19535-2-chris@chris-wilson.co.uk>

On Sun, Jan 10, 2021 at 03:03:55PM +0000, Chris Wilson wrote:
> The mitigation is required for all gen7 platforms, now that it does not
> cause GPU hangs, restore it for Ivybridge and Baytrail.
> 
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 1c6d421f6fe5..724d56c9583d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1324,7 +1324,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
>  
>  	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
>  
> -	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
> +	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {

when CI is really happy

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  		err = gen7_ctx_switch_bb_init(engine);
>  		if (err)
>  			goto err_ring_unpin;
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2021-01-11 17:35 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-10 15:03 [Intel-gfx] [PATCH 01/11] drm/i915/gt: Limit VFE threads based on GT Chris Wilson
2021-01-10 15:03 ` [Intel-gfx] [PATCH 02/11] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail Chris Wilson
2021-01-11 17:35   ` Rodrigo Vivi [this message]
2021-01-10 15:03 ` [Intel-gfx] [PATCH 03/11] drm/i915: Allow the sysadmin to override security mitigations Chris Wilson
2021-01-11 17:31   ` Bloomfield, Jon
2021-01-11 17:48   ` Rodrigo Vivi
2021-01-11 20:58   ` Abodunrin, Akeem G
2021-01-11 21:10     ` Chris Wilson
2021-01-10 15:03 ` [Intel-gfx] [PATCH 04/11] drm/i915/gt: Rearrange vlv workarounds Chris Wilson
2021-01-10 15:03 ` [Intel-gfx] [PATCH 05/11] drm/i915/gt: Rearrange ivb workarounds Chris Wilson
2021-01-10 15:03 ` [Intel-gfx] [PATCH 06/11] drm/i915/gt: Replace open-coded intel_engine_stop_cs() Chris Wilson
2021-01-10 15:04 ` [Intel-gfx] [PATCH 07/11] drm/i915/gt: Reapply ppgtt enabling after engine resets Chris Wilson
2021-01-10 15:04 ` [Intel-gfx] [PATCH 08/11] drm/i915/gt: Lift stop_ring() to reset_prepare Chris Wilson
2021-01-10 15:04 ` [Intel-gfx] [PATCH 09/11] drm/i915/gt: Pull ring submission resume under its caller forcewake Chris Wilson
2021-01-10 15:04 ` [Intel-gfx] [PATCH 10/11] drm/i915/selftests: Prepare the selftests for engine resets with ring submission Chris Wilson
2021-01-10 15:04 ` [Intel-gfx] [PATCH 11/11] drm/i915: Mark per-engine-reset as supported on gen7 Chris Wilson
2021-01-10 15:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/11] drm/i915/gt: Limit VFE threads based on GT Patchwork
2021-01-10 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-10 16:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-11 17:35 ` [Intel-gfx] [PATCH 01/11] " Rodrigo Vivi
2021-01-11 20:51   ` Chris Wilson
2021-01-11 21:04     ` Rodrigo Vivi

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