From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
Date: Mon, 1 Feb 2021 15:01:33 -0800 [thread overview]
Message-ID: <20210201230133.19221-1-anusha.srivatsa@intel.com> (raw)
Add support to load GuC and HuC firmware for Dg1.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 984fa79e0fa7..0e63881674a4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,6 +48,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* firmware as TGL.
*/
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+ fw_def(DG1, 0, guc_def(dg1, 49, 0, 1), huc_def(dg1, 7, 7, 1)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \
--
2.25.0
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next reply other threads:[~2021-02-01 23:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 23:01 Anusha Srivatsa [this message]
2021-02-01 23:04 ` [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support Chris Wilson
2021-02-01 23:19 ` Srivatsa, Anusha
2021-02-01 23:22 ` Chris Wilson
2021-02-02 0:46 ` Srivatsa, Anusha
2021-02-01 23:53 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg1: Add GuC and HuC support (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-01-30 19:40 [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support Anusha Srivatsa
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