From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Do not set any power wells when there is no display
Date: Tue, 30 Mar 2021 09:58:33 -0700 [thread overview]
Message-ID: <20210330165833.GB4484@InViCtUs> (raw)
In-Reply-To: <20210322205805.62205-2-jose.souza@intel.com>
On Mon, Mar 22, 2021 at 01:58:04PM -0700, José Roberto de Souza wrote:
> Power wells are only part of display block and not necessary when
> running a headless driver.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e0eaa872350..e6a3b3e6b1f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4673,7 +4673,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
> - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> + if (!HAS_DISPLAY(dev_priv)) {
> + power_domains->power_well_count = 0;
> + err = 0;
> + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> err = set_power_wells_mask(power_domains, tgl_power_wells,
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> } else if (IS_ROCKETLAKE(dev_priv)) {
> --
> 2.31.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-03-30 16:58 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-22 20:58 [Intel-gfx] [PATCH v2 1/3] drm/i915: Skip display interruption setup when display is not available José Roberto de Souza
2021-03-22 20:58 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Do not set any power wells when there is no display José Roberto de Souza
2021-03-30 16:58 ` Sripada, Radhakrishna [this message]
2021-03-22 20:58 ` [Intel-gfx] [PATCH v2 3/3] drm/i915: skip display initialization " José Roberto de Souza
2021-03-30 17:00 ` Sripada, Radhakrishna
2021-03-23 0:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915: Skip display interruption setup when display is not available Patchwork
2021-03-23 22:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-03-30 16:57 ` [Intel-gfx] [PATCH v2 1/3] " Sripada, Radhakrishna
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210330165833.GB4484@InViCtUs \
--to=radhakrishna.sripada@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=jose.souza@intel.com \
--cc=lucas.demarchi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox