From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 03/19] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
Date: Fri, 14 May 2021 08:36:55 -0700 [thread overview]
Message-ID: <20210514153711.2359617-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210514153711.2359617-1-matthew.d.roper@intel.com>
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 861409bc210d..d283c420af3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1097,10 +1097,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1188,7 +1196,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1198,14 +1205,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
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next prev parent reply other threads:[~2021-05-14 15:37 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 15:36 [Intel-gfx] [CI 00/19] Another batch of reviewed XeLPD / ADL-P patches Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 01/19] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-05-14 15:36 ` Matt Roper [this message]
2021-05-14 15:36 ` [Intel-gfx] [CI 04/19] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 05/19] drm/i915: Get slice height before computing rc params Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 06/19] drm/i915/xelpd: Provide port/phy mapping for vbt Matt Roper
2021-05-14 15:36 ` [Intel-gfx] [CI 07/19] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 08/19] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 09/19] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 10/19] drm/i915/adl_p: Enable modular fia Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 11/19] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 12/19] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 13/19] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 14/19] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-06-03 9:39 ` Jani Nikula
2021-06-03 12:33 ` Jani Nikula
2021-06-03 13:49 ` Manna, Animesh
2021-06-03 18:27 ` Navare, Manasi
2021-06-04 9:11 ` Jani Nikula
2021-06-03 13:37 ` Manna, Animesh
2021-06-03 15:41 ` Jani Nikula
2021-06-04 8:54 ` Manna, Animesh
2021-05-14 15:37 ` [Intel-gfx] [CI 16/19] drm/i915/adl_p: Add IPs stepping mapping Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 17/19] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 18/19] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-05-14 15:37 ` [Intel-gfx] [CI 19/19] drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057) Matt Roper
2021-05-14 16:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Another batch of reviewed XeLPD / ADL-P patches Patchwork
2021-05-14 16:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-14 17:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15 2:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-15 3:00 ` Matt Roper
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