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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 10/17] drm/i915/guc: Replace CTB array with explicit members
Date: Tue, 25 May 2021 14:15:34 -0700	[thread overview]
Message-ID: <20210525211541.87696-11-matthew.brost@intel.com> (raw)
In-Reply-To: <20210525211541.87696-1-matthew.brost@intel.com>

From: Michal Wajdeczko <michal.wajdeczko@intel.com>

Upcoming GuC firmware will always require just two CTBs and we
also plan to configure them with different sizes, so definining
them as array is no longer suitable.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ++++++++++++-----------
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  7 +++-
 2 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index fbd6bd20f588..c54a29176862 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -168,10 +168,10 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
 	struct intel_guc *guc = ct_to_guc(ct);
 	struct guc_ct_buffer_desc *desc;
 	u32 blob_size;
+	u32 cmds_size;
 	void *blob;
 	u32 *cmds;
 	int err;
-	int i;
 
 	GEM_BUG_ON(ct->vma);
 
@@ -207,15 +207,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
 
 	CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);
 
-	/* store pointers to desc and cmds */
-	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
-		GEM_BUG_ON((i !=  CTB_SEND) && (i != CTB_RECV));
+	/* store pointers to desc and cmds for send ctb */
+	desc = blob;
+	cmds = blob + PAGE_SIZE / 2;
+	cmds_size = PAGE_SIZE / 4;
+	CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "send",
+		 ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
 
-		desc = blob + PAGE_SIZE / 4 * i;
-		cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
+	guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size);
 
-		guc_ct_buffer_init(&ct->ctbs[i], desc, cmds, PAGE_SIZE / 4);
-	}
+	/* store pointers to desc and cmds for recv ctb */
+	desc = blob + PAGE_SIZE / 4;
+	cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
+	cmds_size = PAGE_SIZE / 4;
+	CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "recv",
+		 ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
+
+	guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size);
 
 	return 0;
 }
@@ -246,7 +254,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	u32 base, cmds;
 	void *blob;
 	int err;
-	int i;
 
 	GEM_BUG_ON(ct->enabled);
 
@@ -257,28 +264,25 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 
 	/* blob should start with send descriptor */
 	blob = __px_vaddr(ct->vma->obj);
-	GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
+	GEM_BUG_ON(blob != ct->ctbs.send.desc);
 
 	/* (re)initialize descriptors */
-	for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
-		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
+	cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+	guc_ct_buffer_reset(&ct->ctbs.send, cmds);
 
-		cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
-		CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
-
-		guc_ct_buffer_reset(&ct->ctbs[i], cmds);
-	}
+	cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+	guc_ct_buffer_reset(&ct->ctbs.recv, cmds);
 
 	/*
 	 * Register both CT buffers starting with RECV buffer.
 	 * Descriptors are in first half of the blob.
 	 */
-	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc, blob),
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.recv.desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_RECV);
 	if (unlikely(err))
 		goto err_out;
 
-	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc, blob),
+	err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.send.desc, blob),
 				 INTEL_GUC_CT_BUFFER_TYPE_SEND);
 	if (unlikely(err))
 		goto err_deregister;
@@ -341,7 +345,7 @@ static int ct_write(struct intel_guc_ct *ct,
 		    u32 len /* in dwords */,
 		    u32 fence)
 {
-	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
+	struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
 	struct guc_ct_buffer_desc *desc = ctb->desc;
 	u32 head = desc->head;
 	u32 tail = desc->tail;
@@ -557,7 +561,7 @@ static inline bool ct_header_is_response(u32 header)
 
 static int ct_read(struct intel_guc_ct *ct, u32 *data)
 {
-	struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
+	struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
 	struct guc_ct_buffer_desc *desc = ctb->desc;
 	u32 head = desc->head;
 	u32 tail = desc->tail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 4009e2dd0de4..fc9486779e87 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -47,8 +47,11 @@ struct intel_guc_ct {
 	struct i915_vma *vma;
 	bool enabled;
 
-	/* buffers for sending(0) and receiving(1) commands */
-	struct intel_guc_ct_buffer ctbs[2];
+	/* buffers for sending and receiving commands */
+	struct {
+		struct intel_guc_ct_buffer send;
+		struct intel_guc_ct_buffer recv;
+	} ctbs;
 
 	struct {
 		u32 last_fence; /* last fence used to send request */
-- 
2.28.0

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  parent reply	other threads:[~2021-05-25 20:58 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25 21:15 [Intel-gfx] [PATCH 00/17] Non-interface changing GuC CTBs updates Matthew Brost
2021-05-25 21:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-05-25 21:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-25 21:15 ` [Intel-gfx] [PATCH 01/17] drm/i915/guc: skip disabling CTBs before sanitizing the GuC Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 02/17] drm/i915/guc: use probe_error log for CT enablement failure Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 03/17] drm/i915/guc: enable only the user interrupt when using GuC submission Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 04/17] drm/i915/guc: Remove sample_forcewake h2g action Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 05/17] drm/i915/guc: Keep strict GuC ABI definitions Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 06/17] drm/i915/guc: Stop using fence/status from CTB descriptor Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 07/17] drm/i915: Promote ptrdiff() to i915_utils.h Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 08/17] drm/i915/guc: Only rely on own CTB size Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 09/17] drm/i915/guc: Don't repeat CTB layout calculations Matthew Brost
2021-05-25 21:15 ` Matthew Brost [this message]
2021-05-25 21:15 ` [Intel-gfx] [PATCH 11/17] drm/i915/guc: Update sizes of CTB buffers Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 12/17] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 13/17] drm/i915/guc: Start protecting access to CTB descriptors Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 14/17] drm/i915/guc: Ensure H2G buffer updates visible before tail update Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 15/17] drm/i915/guc: Stop using mutex while sending CTB messages Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 16/17] drm/i915/guc: Don't receive all G2H messages in irq handler Matthew Brost
2021-05-25 21:15 ` [Intel-gfx] [PATCH 17/17] drm/i915/guc: Always copy CT message to new allocation Matthew Brost
2021-05-25 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Non-interface changing GuC CTBs updates Patchwork
2021-05-26  3:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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