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From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	dri-devel@lists.freedesktop.org,
	"Kenneth Graunke" <kenneth@whitecape.org>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>
Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/uapi: reject set_domain for discrete
Date: Thu,  1 Jul 2021 16:10:19 +0100	[thread overview]
Message-ID: <20210701151019.1103315-3-matthew.auld@intel.com> (raw)
In-Reply-To: <20210701151019.1103315-1-matthew.auld@intel.com>

The CPU domain should be static for discrete, and on DG1 we don't need
any flushing since everything is already coherent, so really all this
does is an object wait, for which we have an ioctl. Longer term the
desired caching should be an immutable creation time property for the
BO, which can be set with something like gem_create_ext.

One other user is iris + userptr, which uses the set_domain to probe all
the pages to check if the GUP succeeds, however keeping the set_domain
around just for that seems rather scuffed. We could equally just submit
a dummy batch, which should hopefully be good enough, otherwise adding a
new creation time flag for userptr might be an option. Although longer
term we will also have vm_bind, which should also be a nice fit for
this, so adding a whole new flag is likely overkill.

Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 43004bef55cb..b684a62bf3b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	u32 write_domain = args->write_domain;
 	int err;
 
+	if (IS_DGFX(to_i915(dev)))
+		return -ENODEV;
+
 	/* Only handle setting domains to types used by the CPU. */
 	if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
 		return -EINVAL;
-- 
2.26.3

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  parent reply	other threads:[~2021-07-01 15:10 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-01 15:10 [Intel-gfx] [PATCH v2 1/3] drm/i915: use consistent CPU mappings for pin_map users Matthew Auld
2021-07-01 15:10 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/uapi: reject caching ioctls for discrete Matthew Auld
2021-07-01 15:10 ` Matthew Auld [this message]
2021-07-02 13:21   ` [Intel-gfx] [PATCH v2 3/3] drm/i915/uapi: reject set_domain " Matthew Auld
2021-07-02 14:31   ` Tvrtko Ursulin
2021-07-02 19:22     ` Daniel Vetter
2021-07-05  8:34       ` Tvrtko Ursulin
2021-07-05 14:25         ` Daniel Vetter
2021-07-05 14:55           ` Tvrtko Ursulin
2021-07-13  2:20       ` Kenneth Graunke
2021-07-01 15:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm/i915: use consistent CPU mappings for pin_map users Patchwork
2021-07-01 16:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-01 18:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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