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From: Matthew Brost <matthew.brost@intel.com>
To: John Harrison <john.c.harrison@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
Date: Sat, 17 Jul 2021 04:09:27 +0000	[thread overview]
Message-ID: <20210717040927.GA11555@DUT151-ICLU.fm.intel.com> (raw)
In-Reply-To: <20210710035502.GA187444@DUT030-TGLY.fm.intel.com>

On Sat, Jul 10, 2021 at 03:55:02AM +0000, Matthew Brost wrote:
> On Fri, Jul 09, 2021 at 05:16:34PM -0700, John Harrison wrote:
> > On 6/24/2021 00:04, Matthew Brost wrote:
> > > When running the GuC the GPU can't be considered idle if the GuC still
> > > has contexts pinned. As such, a call has been added in
> > > intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
> > > the number of unpinned contexts to go to zero.
> > > 
> > > v2: rtimeout -> remaining_timeout
> > > 
> > > Cc: John Harrison <john.c.harrison@intel.com>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/gem/i915_gem_mman.c      |  3 +-
> > >   drivers/gpu/drm/i915/gt/intel_gt.c            | 19 ++++
> > >   drivers/gpu/drm/i915/gt/intel_gt.h            |  2 +
> > >   drivers/gpu/drm/i915/gt/intel_gt_requests.c   | 22 ++---
> > >   drivers/gpu/drm/i915/gt/intel_gt_requests.h   |  9 +-
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  4 +
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c     |  1 +
> > >   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h     |  4 +
> > >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 88 ++++++++++++++++++-
> > >   drivers/gpu/drm/i915/gt/uc/intel_uc.h         |  5 ++
> > >   drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
> > >   drivers/gpu/drm/i915/i915_gem_evict.c         |  1 +
> > >   .../gpu/drm/i915/selftests/igt_live_test.c    |  2 +-
> > >   .../gpu/drm/i915/selftests/mock_gem_device.c  |  3 +-
> > >   14 files changed, 137 insertions(+), 27 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > index 2fd155742bd2..335b955d5b4b 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > @@ -644,7 +644,8 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
> > >   		goto insert;
> > >   	/* Attempt to reap some mmap space from dead objects */
> > > -	err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT);
> > > +	err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT,
> > > +					       NULL);
> > >   	if (err)
> > >   		goto err;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index e714e21c0a4d..acfdd53b2678 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -585,6 +585,25 @@ static void __intel_gt_disable(struct intel_gt *gt)
> > >   	GEM_BUG_ON(intel_gt_pm_is_awake(gt));
> > >   }
> > > +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> > > +{
> > > +	long remaining_timeout;
> > > +
> > > +	/* If the device is asleep, we have no requests outstanding */
> > > +	if (!intel_gt_pm_is_awake(gt))
> > > +		return 0;
> > > +
> > > +	while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
> > > +							   &remaining_timeout)) > 0) {
> > > +		cond_resched();
> > > +		if (signal_pending(current))
> > > +			return -EINTR;
> > > +	}
> > > +
> > > +	return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
> > > +							  remaining_timeout);
> > > +}
> > > +
> > >   int intel_gt_init(struct intel_gt *gt)
> > >   {
> > >   	int err;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> > > index e7aabe0cc5bf..74e771871a9b 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> > > @@ -48,6 +48,8 @@ void intel_gt_driver_release(struct intel_gt *gt);
> > >   void intel_gt_driver_late_release(struct intel_gt *gt);
> > > +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> > > +
> > >   void intel_gt_check_and_clear_faults(struct intel_gt *gt);
> > >   void intel_gt_clear_error_registers(struct intel_gt *gt,
> > >   				    intel_engine_mask_t engine_mask);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > index 647eca9d867a..39f5e824dac5 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> > > @@ -13,6 +13,7 @@
> > >   #include "intel_gt_pm.h"
> > >   #include "intel_gt_requests.h"
> > >   #include "intel_timeline.h"
> > > +#include "uc/intel_uc.h"
> > Why is this needed?
> > 
> 
> It is not, likely holdover from internal churn.
> 
> > >   static bool retire_requests(struct intel_timeline *tl)
> > >   {
> > > @@ -130,7 +131,8 @@ void intel_engine_fini_retire(struct intel_engine_cs *engine)
> > >   	GEM_BUG_ON(engine->retire);
> > >   }
> > > -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
> > > +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
> > > +				      long *remaining_timeout)
> > >   {
> > >   	struct intel_gt_timelines *timelines = &gt->timelines;
> > >   	struct intel_timeline *tl, *tn;
> > > @@ -195,22 +197,10 @@ out_active:	spin_lock(&timelines->lock);
> > >   	if (flush_submission(gt, timeout)) /* Wait, there's more! */
> > >   		active_count++;
> > > -	return active_count ? timeout : 0;
> > > -}
> > > -
> > > -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> > > -{
> > > -	/* If the device is asleep, we have no requests outstanding */
> > > -	if (!intel_gt_pm_is_awake(gt))
> > > -		return 0;
> > > -
> > > -	while ((timeout = intel_gt_retire_requests_timeout(gt, timeout)) > 0) {
> > > -		cond_resched();
> > > -		if (signal_pending(current))
> > > -			return -EINTR;
> > > -	}
> > > +	if (remaining_timeout)
> > > +		*remaining_timeout = timeout;
> > > -	return timeout;
> > > +	return active_count ? timeout : 0;
> > >   }
> > >   static void retire_work_handler(struct work_struct *work)
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > index fcc30a6e4fe9..51dbe0e3294e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > @@ -6,14 +6,17 @@
> > >   #ifndef INTEL_GT_REQUESTS_H
> > >   #define INTEL_GT_REQUESTS_H
> > > +#include <stddef.h>
> > > +
> > Why is this needed?
> > 
> 
> I swear I needed stddef.h for NULL on a different machice of mine. It
> seems to be quite happy without it on my current machine. Can remove.
> 

And it in fact does need to be included. See CI results below:
https://patchwork.freedesktop.org/series/91840/#rev3

Matt

> > >   struct intel_engine_cs;
> > >   struct intel_gt;
> > >   struct intel_timeline;
> > > -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout);
> > > +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
> > > +				      long *remaining_timeout);
> > >   static inline void intel_gt_retire_requests(struct intel_gt *gt)
> > >   {
> > > -	intel_gt_retire_requests_timeout(gt, 0);
> > > +	intel_gt_retire_requests_timeout(gt, 0, NULL);
> > >   }
> > >   void intel_engine_init_retire(struct intel_engine_cs *engine);
> > > @@ -21,8 +24,6 @@ void intel_engine_add_retire(struct intel_engine_cs *engine,
> > >   			     struct intel_timeline *tl);
> > >   void intel_engine_fini_retire(struct intel_engine_cs *engine);
> > > -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> > > -
> > >   void intel_gt_init_requests(struct intel_gt *gt);
> > >   void intel_gt_park_requests(struct intel_gt *gt);
> > >   void intel_gt_unpark_requests(struct intel_gt *gt);
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > index 24e7a924134e..22eb1e9cca41 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > @@ -38,6 +38,8 @@ struct intel_guc {
> > >   	spinlock_t irq_lock;
> > >   	unsigned int msg_enabled_mask;
> > > +	atomic_t outstanding_submission_g2h;
> > > +
> > >   	struct {
> > >   		void (*reset)(struct intel_guc *guc);
> > >   		void (*enable)(struct intel_guc *guc);
> > > @@ -238,6 +240,8 @@ static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
> > >   	spin_unlock_irq(&guc->irq_lock);
> > >   }
> > > +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout);
> > > +
> > >   int intel_guc_reset_engine(struct intel_guc *guc,
> > >   			   struct intel_engine_cs *engine);
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > index a60970e85635..e0f92e28350c 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > > @@ -109,6 +109,7 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> > >   	INIT_LIST_HEAD(&ct->requests.incoming);
> > >   	INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
> > >   	tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func);
> > > +	init_waitqueue_head(&ct->wq);
> > >   }
> > >   static inline const char *guc_ct_buffer_type_to_str(u32 type)
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > > index 660bf37238e2..ab1b79ab960b 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> > > @@ -10,6 +10,7 @@
> > >   #include <linux/spinlock.h>
> > >   #include <linux/workqueue.h>
> > >   #include <linux/ktime.h>
> > > +#include <linux/wait.h>
> > >   #include "intel_guc_fwif.h"
> > > @@ -68,6 +69,9 @@ struct intel_guc_ct {
> > >   	struct tasklet_struct receive_tasklet;
> > > +	/** @wq: wait queue for g2h chanenl */
> > > +	wait_queue_head_t wq;
> > > +
> > >   	struct {
> > >   		u16 last_fence; /* last fence used to send request */
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index ef24758c4266..d1a28283a9ae 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -254,6 +254,74 @@ static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
> > >   	xa_store_irq(&guc->context_lookup, id, ce, GFP_ATOMIC);
> > >   }
> > > +static int guc_submission_busy_loop(struct intel_guc* guc,
> > I think this name is misleading. It would be better as
> > guc_submission_send_busy_loop.
> > 
> 
> Yep, better name. Will fix.
> 
> > > +				    const u32 *action,
> > > +				    u32 len,
> > > +				    u32 g2h_len_dw,
> > > +				    bool loop)
> > > +{
> > > +	int err;
> > > +
> > > +	err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
> > > +
> > > +	if (!err && g2h_len_dw)
> > > +		atomic_inc(&guc->outstanding_submission_g2h);
> > > +
> > > +	return err;
> > > +}
> > > +
> > > +static int guc_wait_for_pending_msg(struct intel_guc *guc,
> > > +				    atomic_t *wait_var,
> > > +				    bool interruptible,
> > > +				    long timeout)
> > > +{
> > > +	const int state = interruptible ?
> > > +		TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> > > +	DEFINE_WAIT(wait);
> > > +
> > > +	might_sleep();
> > > +	GEM_BUG_ON(timeout < 0);
> > > +
> > > +	if (!atomic_read(wait_var))
> > > +		return 0;
> > > +
> > > +	if (!timeout)
> > > +		return -ETIME;
> > > +
> > > +	for (;;) {
> > > +		prepare_to_wait(&guc->ct.wq, &wait, state);
> > > +
> > > +		if (!atomic_read(wait_var))
> > > +			break;
> > > +
> > > +		if (signal_pending_state(state, current)) {
> > > +			timeout = -ERESTARTSYS;
> > > +			break;
> > > +		}
> > > +
> > > +		if (!timeout) {
> > > +			timeout = -ETIME;
> > > +			break;
> > > +		}
> > > +
> > > +		timeout = io_schedule_timeout(timeout);
> > > +	}
> > > +	finish_wait(&guc->ct.wq, &wait);
> > > +
> > > +	return (timeout < 0) ? timeout : 0;
> > > +}
> > > +
> > > +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
> > > +{
> > > +	bool interruptible = true;
> > > +
> > > +	if (unlikely(timeout < 0))
> > > +		timeout = -timeout, interruptible = false;
> > Why is this a comma bridged statement rather than just two lines with braces
> > on the if?
> > 
> > And overloading negative timeouts to mean non-interruptible seems
> > unnecessarily convoluted in the first place. Why not just have an
> > interruptible parameter? I'm also not seeing how the timeout gets to be
> > negative in the first place?
> >
> 
> Copy paste from some other code, can remove the comma and replace with 2
> lines.
> 
> This is how intel_gt_wait_for_idle works which in turn calls this. Not
> saying the negative parameter meaning something special is right, just
> how it is currently done. Now that you mention this with the
> remaining_timeout I may have broken this too. How about I just add
> parameter than this convoluted sceme as you suggest.
>  
> > 
> > > +
> > > +	return guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
> > > +					interruptible, timeout);
> > > +}
> > > +
> > >   static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
> > >   {
> > >   	int err;
> > > @@ -280,6 +348,7 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
> > >   	err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
> > >   	if (!enabled && !err) {
> > > +		atomic_inc(&guc->outstanding_submission_g2h);
> > >   		set_context_enabled(ce);
> > >   	} else if (!enabled) {
> > >   		clr_context_pending_enable(ce);
> > > @@ -731,7 +800,7 @@ static int __guc_action_register_context(struct intel_guc *guc,
> > >   		offset,
> > >   	};
> > > -	return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> > > +	return guc_submission_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> > >   }
> > >   static int register_context(struct intel_context *ce)
> > > @@ -751,7 +820,7 @@ static int __guc_action_deregister_context(struct intel_guc *guc,
> > >   		guc_id,
> > >   	};
> > > -	return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
> > > +	return guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
> > >   					G2H_LEN_DW_DEREGISTER_CONTEXT, true);
> > >   }
> > > @@ -868,7 +937,9 @@ static int guc_context_pin(struct intel_context *ce, void *vaddr)
> > >   static void guc_context_unpin(struct intel_context *ce)
> > >   {
> > > -	unpin_guc_id(ce_to_guc(ce), ce);
> > > +	struct intel_guc *guc = ce_to_guc(ce);
> > > +
> > > +	unpin_guc_id(guc, ce);
> > Should this be part of this patch?
> > 
> 
> Not likely. Let me see what is going on here.
> 
> > >   	lrc_unpin(ce);
> > >   }
> > > @@ -891,7 +962,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
> > >   	intel_context_get(ce);
> > > -	intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
> > > +	guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
> > >   				 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
> > >   }
> > > @@ -1433,6 +1504,12 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
> > >   	return ce;
> > >   }
> > > +static void decr_outstanding_submission_g2h(struct intel_guc *guc)
> > > +{
> > > +	if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
> > > +		wake_up_all(&guc->ct.wq);
> > > +}
> > > +
> > >   int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> > >   					  const u32 *msg,
> > >   					  u32 len)
> > > @@ -1468,6 +1545,8 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> > >   		lrc_destroy(&ce->ref);
> > >   	}
> > > +	decr_outstanding_submission_g2h(guc);
> > > +
> > >   	return 0;
> > >   }
> > > @@ -1516,6 +1595,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> > >   		spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> > >   	}
> > > +	decr_outstanding_submission_g2h(guc);
> > >   	intel_context_put(ce);
> > >   	return 0;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> > > index 9c954c589edf..c4cef885e984 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> > > @@ -81,6 +81,11 @@ uc_state_checkers(guc, guc_submission);
> > >   #undef uc_state_checkers
> > >   #undef __uc_state_checker
> > > +static inline int intel_uc_wait_for_idle(struct intel_uc *uc, long timeout)
> > > +{
> > > +	return intel_guc_wait_for_idle(&uc->guc, timeout);
> > > +}
> > > +
> > >   #define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
> > >   static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
> > >   { \
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index cc745751ac53..277800987bf8 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -36,6 +36,7 @@
> > >   #include "gt/intel_gt_clock_utils.h"
> > >   #include "gt/intel_gt.h"
> > >   #include "gt/intel_gt_pm.h"
> > > +#include "gt/intel_gt.h"
> > All of these extra includes seem incorrect. There is no code change in any
> > of the files below that would warrant a new include.
> > 
> 
> Well this is surely wrong as it is included two lines above. Will fix.
> 
> Matt
> 
> > John.
> > 
> > 
> > >   #include "gt/intel_gt_requests.h"
> > >   #include "gt/intel_reset.h"
> > >   #include "gt/intel_rc6.h"
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
> > > index 4d2d59a9942b..2b73ddb11c66 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> > > @@ -27,6 +27,7 @@
> > >    */
> > >   #include "gem/i915_gem_context.h"
> > > +#include "gt/intel_gt.h"
> > >   #include "gt/intel_gt_requests.h"
> > >   #include "i915_drv.h"
> > > diff --git a/drivers/gpu/drm/i915/selftests/igt_live_test.c b/drivers/gpu/drm/i915/selftests/igt_live_test.c
> > > index c130010a7033..1c721542e277 100644
> > > --- a/drivers/gpu/drm/i915/selftests/igt_live_test.c
> > > +++ b/drivers/gpu/drm/i915/selftests/igt_live_test.c
> > > @@ -5,7 +5,7 @@
> > >    */
> > >   #include "i915_drv.h"
> > > -#include "gt/intel_gt_requests.h"
> > > +#include "gt/intel_gt.h"
> > >   #include "../i915_selftest.h"
> > >   #include "igt_flush_test.h"
> > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > index d189c4bd4bef..4f8180146888 100644
> > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > @@ -52,7 +52,8 @@ void mock_device_flush(struct drm_i915_private *i915)
> > >   	do {
> > >   		for_each_engine(engine, gt, id)
> > >   			mock_engine_flush(engine);
> > > -	} while (intel_gt_retire_requests_timeout(gt, MAX_SCHEDULE_TIMEOUT));
> > > +	} while (intel_gt_retire_requests_timeout(gt, MAX_SCHEDULE_TIMEOUT,
> > > +						  NULL));
> > >   }
> > >   static void mock_device_release(struct drm_device *dev)
> > 
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  reply	other threads:[~2021-07-17  4:09 UTC|newest]

Thread overview: 170+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24  7:04 [Intel-gfx] [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 17:23   ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-25 11:58   ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 13:49   ` Michal Wajdeczko
2021-06-24 15:41     ` Matthew Brost
2021-06-25 12:03       ` Michal Wajdeczko
2021-06-24  7:04 ` [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 14:48   ` Michal Wajdeczko
2021-06-24 15:49     ` Matthew Brost
2021-06-24 17:02       ` Michal Wajdeczko
2021-06-24 22:41         ` Matthew Brost
2021-06-25 11:50           ` Michal Wajdeczko
2021-06-25 17:53             ` Matthew Brost
2021-06-24 22:47         ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 17:37   ` Michal Wajdeczko
2021-06-24 23:01     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-25 13:09   ` Michal Wajdeczko
2021-06-25 18:26     ` Matthew Brost
2021-06-25 20:28     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-29 21:11   ` John Harrison
2021-06-30  0:30     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-25 19:44   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-25 13:17   ` Michal Wajdeczko
2021-06-25 17:26     ` Matthew Brost
2021-06-29 21:20       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-29 22:04   ` John Harrison
2021-06-30  0:41     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-29 22:09   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-25 13:25   ` Michal Wajdeczko
2021-06-25 17:46     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-09 22:39   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-09 22:48   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-09 22:53   ` John Harrison
2021-07-10  3:00     ` Matthew Brost
2021-07-12 17:57       ` John Harrison
2021-07-12 18:11         ` Daniel Vetter
2021-06-24  7:04 ` [Intel-gfx] [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-09 22:59   ` John Harrison
2021-07-10  3:36     ` Matthew Brost
2021-07-12 17:54       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-09 23:03   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-15  1:51   ` Daniele Ceraolo Spurio
2021-06-24  7:04 ` [Intel-gfx] [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-09 23:53   ` John Harrison
2021-07-15  0:07     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-13 18:36   ` John Harrison
2021-07-15  0:06     ` Matthew Brost
2021-07-15  0:12       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-10  0:16   ` John Harrison
2021-07-10  3:55     ` Matthew Brost
2021-07-17  4:09       ` Matthew Brost [this message]
2021-06-24  7:04 ` [Intel-gfx] [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-12 18:05   ` John Harrison
2021-07-12 20:59     ` Matthew Brost
2021-07-12 21:37       ` John Harrison
2021-07-13  8:51   ` Michal Wajdeczko
2021-07-14 23:56     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-12 18:08   ` John Harrison
2021-07-13  9:06   ` Tvrtko Ursulin
2021-07-20  1:59     ` Matthew Brost
2021-07-22 13:55       ` Tvrtko Ursulin
2021-06-24  7:04 ` [Intel-gfx] [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-07-12 18:10   ` John Harrison
2021-07-12 21:47     ` Matthew Brost
2021-07-12 21:51       ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-15  1:21   ` Daniele Ceraolo Spurio
2021-06-24  7:04 ` [Intel-gfx] [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-12 18:11   ` John Harrison
2021-07-12 20:06     ` Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 20:05     ` Matthew Brost
2021-07-12 21:36       ` Matthew Brost
2021-07-12 21:48         ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-06-24  7:04 ` [Intel-gfx] [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-12 19:19   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-12 19:58   ` John Harrison
2021-07-15  0:53     ` Matthew Brost
2021-07-15  9:36   ` Tvrtko Ursulin
2021-07-26 22:48     ` Matthew Brost
2021-07-27  8:56       ` Tvrtko Ursulin
2021-07-27 18:30         ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-12 20:11   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-12 22:56   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-12 22:58   ` John Harrison
2021-07-15  0:32     ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-12 22:59   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-12 23:00   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 15:55   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 16:19   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-12 23:05   ` John Harrison
2021-06-24  7:05 ` [Intel-gfx] [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-15  0:43   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-25  0:59   ` Matthew Brost
2021-06-25 19:10     ` John Harrison
2021-07-10 18:56       ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-25  1:10   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 16:34   ` Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24  7:05 ` [Intel-gfx] [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-30  8:22   ` Martin Peres
2021-06-30 18:00     ` Matthew Brost
2021-07-01 18:24       ` Martin Peres
2021-07-02  8:13         ` Martin Peres
2021-07-02 13:06           ` Michal Wajdeczko
2021-07-02 13:12             ` Martin Peres
2021-07-02 14:08               ` Michal Wajdeczko
2021-06-30 18:58     ` John Harrison
2021-07-01  8:14       ` Pekka Paalanen
2021-07-01 18:27         ` Martin Peres
2021-07-01 19:28           ` Daniel Vetter
2021-07-02  7:29             ` Pekka Paalanen
2021-07-02  8:09               ` Martin Peres
2021-07-02 15:07                 ` Michal Wajdeczko
2021-07-03  8:21                   ` Martin Peres
2021-07-07  0:57                     ` John Harrison
2021-07-07  7:47                       ` Pekka Paalanen
2021-07-07 10:11                       ` Michal Wajdeczko
2021-07-15  0:49   ` Matthew Brost
2021-06-24  7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24  7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24  7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22  9:35 ` [Intel-gfx] [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 16:42   ` Matthew Brost
2021-10-25  9:37     ` Joonas Lahtinen
2021-10-25 15:15       ` Matthew Brost
2021-10-26  8:59         ` Joonas Lahtinen
2021-10-26 15:43           ` Matthew Brost
2021-10-26 15:51           ` Matthew Brost
2021-10-27  9:21             ` Joonas Lahtinen
2021-10-25 17:06       ` John Harrison

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