From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Program DFR enable/disable as a GT workaround
Date: Fri, 16 Jul 2021 22:14:22 -0700 [thread overview]
Message-ID: <20210717051426.4120328-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210717051426.4120328-1-matthew.d.roper@intel.com>
DFR programming (which we enable as an optimization on gen11, but must
ensure is disabled on gen12) should be handled as a GT workaround rather
than clock gating initialization. This will ensure that the programming
of these registers is verified with our typical workaround checks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
drivers/gpu/drm/i915/intel_pm.c | 8 --------
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 36d972492883..685c6115d380 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -965,6 +965,12 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /*
+ * This is not a documented workaround, but rather an optimization
+ * to reduce sampler power.
+ */
+ wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
/*
@@ -998,6 +1004,9 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
/* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
wa_14011060649(i915, wal);
+
+ /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
+ wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
static void
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef5304d3c2ec..8a84abfaa4b0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7345,10 +7345,6 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
- /* This is not an Wa. Enable to reduce Sampler power */
- intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
- intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
-
/*Wa_14010594013:icl, ehl */
intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
0, CNL_DELAY_PMRSP);
@@ -7367,10 +7363,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
TGL_VRH_GATING_DIS);
- /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
- intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
- 0, DFR_DISABLE);
-
/* Wa_14013723622:tgl,rkl,dg1,adl-s */
if (DISPLAY_VER(dev_priv) == 12)
intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-17 5:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-17 5:14 [Intel-gfx] [PATCH 0/7] More workaround updates Matt Roper
2021-07-17 5:14 ` [Intel-gfx] [PATCH 1/7] drm/i915: Fix application of WaInPlaceDecompressionHang Matt Roper
2021-07-19 17:51 ` Souza, Jose
2021-07-17 5:14 ` [Intel-gfx] [PATCH 2/7] drm/i915/icl: Drop a couple unnecessary workarounds Matt Roper
2021-07-19 17:55 ` Souza, Jose
2021-07-17 5:14 ` Matt Roper [this message]
2021-07-19 17:57 ` [Intel-gfx] [PATCH 3/7] drm/i915: Program DFR enable/disable as a GT workaround Souza, Jose
2021-07-17 5:14 ` [Intel-gfx] [PATCH 4/7] drm/i915/adl_s: Wa_14011765242 is also needed on A1 display stepping Matt Roper
2021-07-19 17:59 ` Souza, Jose
2021-07-17 5:14 ` [Intel-gfx] [PATCH 5/7] drm/i915/rkl: Wa_1409767108 also applies to RKL Matt Roper
2021-07-19 18:00 ` Souza, Jose
2021-07-17 5:14 ` [Intel-gfx] [PATCH 6/7] drm/i915/rkl: Wa_1408330847 no longer " Matt Roper
2021-07-19 17:37 ` Souza, Jose
2021-07-17 5:14 ` [Intel-gfx] [PATCH 7/7] drm/i915: Make workaround upper bounds exclusive Matt Roper
2021-07-19 17:46 ` Souza, Jose
2021-08-10 12:58 ` Jani Nikula
2021-08-10 13:57 ` Vivi, Rodrigo
2021-07-17 5:41 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for More workaround updates Patchwork
2021-07-17 6:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-17 16:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-21 18:24 ` Matt Roper
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210717051426.4120328-4-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox