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From: Lee Shawn C <shawn.c.lee@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Cooper Chiou <cooper.chiou@intel.com>,
	William Tseng <william.tseng@intel.com>
Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Get proper min cdclk if vDSC enabled
Date: Mon, 19 Jul 2021 15:22:22 +0800	[thread overview]
Message-ID: <20210719072222.13369-6-shawn.c.lee@intel.com> (raw)
In-Reply-To: <20210719072222.13369-1-shawn.c.lee@intel.com>

VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 71067a62264d..c33d574eb991 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2159,6 +2159,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	/* Account for additional needs from the planes */
 	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
+	/*
+	 * VDSC engine can process only 1 pixel per Cd clock.
+	 * In case VDSC is used and max slice count == 1,
+	 * max supported pixel clock should be 100% of CD clock.
+	 * Then do min_cdclk and pixel clock comparison to get cdclk.
+	 */
+	if (DISPLAY_VER(dev_priv) >= 11 &&
+	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+	    crtc_state->dsc.compression_enable &&
+	    crtc_state->dsc.slice_count == 1)
+		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
 	/*
 	 * HACK. Currently for TGL platforms we calculate
 	 * min_cdclk initially based on pixel_rate divided
-- 
2.17.1

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  parent reply	other threads:[~2021-07-19  7:16 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-19  7:22 [Intel-gfx] [PATCH 0/5] MIPI DSI driver enhancements Lee Shawn C
2021-07-19  7:22 ` [Intel-gfx] [PATCH 1/5] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-19  7:22 ` [Intel-gfx] [PATCH 2/5] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
2021-07-19  7:22 ` [Intel-gfx] [PATCH 3/5] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-07-19  7:22 ` [Intel-gfx] [PATCH 4/5] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-07-19  7:22 ` Lee Shawn C [this message]
2021-07-20 12:46   ` [Intel-gfx] [PATCH 5/5] drm/i915: Get proper min cdclk if vDSC enabled Kulkarni, Vandita
2021-07-20 14:30     ` Lee, Shawn C
2021-07-22  7:17       ` Kulkarni, Vandita
2021-07-19  7:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for MIPI DSI driver enhancements Patchwork
2021-07-19  7:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-07-19  8:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-19 10:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-07-22  9:37 ` [Intel-gfx] [PATCH v2 0/5] " Lee Shawn C
2021-07-22  9:37   ` [Intel-gfx] [PATCH v2 1/5] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-22  9:37   ` [Intel-gfx] [PATCH v2 2/5] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
2021-07-22  9:37   ` [Intel-gfx] [PATCH v2 3/5] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-07-22  9:37   ` [Intel-gfx] [PATCH v2 4/5] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-07-22  9:37   ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C

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