From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Add DG1 GuC / HuC firmware defs
Date: Mon, 2 Aug 2021 22:11:20 -0700 [thread overview]
Message-ID: <20210803051121.72017-4-matthew.brost@intel.com> (raw)
In-Reply-To: <20210803051121.72017-1-matthew.brost@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index f8cb00ffb506..a685d563df72 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -51,6 +51,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
+ fw_def(DG1, 0, guc_def(dg1, 62, 0, 0), huc_def(dg1, 7, 9, 3)) \
fw_def(ROCKETLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl, 7, 9, 3)) \
fw_def(JASPERLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl, 9, 0, 0)) \
--
2.28.0
next prev parent reply other threads:[~2021-08-03 4:53 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-03 5:11 [Intel-gfx] [PATCH 0/4] Enable GuC submission by default on DG1 Matthew Brost
2021-08-03 5:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-08-03 5:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-08-03 5:11 ` [Intel-gfx] [PATCH 1/4] drm/i915: Do not define vma on stack Matthew Brost
2021-08-04 19:37 ` Matthew Brost
2021-08-03 5:11 ` [Intel-gfx] [PATCH 2/4] drm/i915/guc: put all guc objects in lmem when available Matthew Brost
2021-08-06 18:43 ` John Harrison
2021-08-03 5:11 ` Matthew Brost [this message]
2021-08-06 18:43 ` [Intel-gfx] [PATCH 3/4] drm/i915/guc: Add DG1 GuC / HuC firmware defs John Harrison
2021-08-03 5:11 ` [Intel-gfx] [PATCH 4/4] drm/i915/guc: Enable GuC submission by default on DG1 Matthew Brost
2021-08-06 18:44 ` John Harrison
2021-08-03 5:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-08-03 12:15 ` [Intel-gfx] [PATCH 0/4] " Daniel Vetter
2021-08-03 17:26 ` Matthew Brost
2021-08-06 11:34 ` Thomas Hellström (Intel)
2021-08-06 12:07 ` Thomas Hellström (Intel)
2021-08-06 16:09 ` Thomas Hellström (Intel)
2021-08-07 17:20 ` Matthew Brost
2021-08-03 16:22 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210803051121.72017-4-matthew.brost@intel.com \
--to=matthew.brost@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox