From: Imre Deak <imre.deak@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
Date: Sat, 18 Sep 2021 00:05:57 +0300 [thread overview]
Message-ID: <20210917210557.GH729837@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20210917205241.231527-1-jose.souza@intel.com>
On Fri, Sep 17, 2021 at 01:52:39PM -0700, José Roberto de Souza wrote:
> Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
> platforms that supports DMC, not only for geminilake and broxton.
According to the spec it's only required for BXT and GLK, see
Bspec 4234, 49193, 49194.
The register description is a bit vague, would need to be clarified
probably.
> While at is also taking the oportunity to simply the code.
>
> BSpec: 7402
> BSpec: 49436
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-------------
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index b0268552b2863..2dc9d632969db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
>
> static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> {
> - u32 val, mask;
> -
> - mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> -
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - mask |= DC_STATE_DEBUG_MASK_CORES;
> -
> /* The below bit doesn't need to be cleared ever afterwards */
> - val = intel_de_read(dev_priv, DC_STATE_DEBUG);
> - if ((val & mask) != mask) {
> - val |= mask;
> - intel_de_write(dev_priv, DC_STATE_DEBUG, val);
> - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> - }
> + intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> + DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> + intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> }
>
> /**
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-09-17 21:06 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
2021-09-23 13:27 ` Gwan-gyeong Mun
2021-09-23 17:25 ` Souza, Jose
2021-09-17 20:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification José Roberto de Souza
2021-09-20 18:12 ` Gwan-gyeong Mun
2021-09-17 21:05 ` Imre Deak [this message]
2021-09-20 19:06 ` [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load Imre Deak
2021-09-17 21:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork
2021-09-17 21:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-17 22:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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