From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request
Date: Mon, 4 Oct 2021 20:05:33 +0300 [thread overview]
Message-ID: <20211004170535.4173-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211004170535.4173-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Print out each DP vswing adjustment request we got from the RX.
Could help in diagnosing what's going on during link training.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 6bab097cafd2..5657be1461ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -343,14 +343,41 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
return v | p;
}
+#define TRAIN_REQ_FMT "%d/%d/%d/%d"
+#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
+ (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
+#define TRAIN_REQ_VSWING_ARGS(link_status) \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
+ _TRAIN_REQ_VSWING_ARGS(link_status, 3)
+#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
+ (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
+#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
+ _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
+
void
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE])
{
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ char phy_name[10];
int lane;
+ drm_dbg_kms(encoder->base.dev, "[ENCODER:%d:%s] lanes: %d, "
+ "vswing request: " TRAIN_REQ_FMT ", "
+ "pre-emphasis request: " TRAIN_REQ_FMT ", at %s\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc_state->lane_count,
+ TRAIN_REQ_VSWING_ARGS(link_status),
+ TRAIN_REQ_PREEMPH_ARGS(link_status),
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+
for (lane = 0; lane < 4; lane++)
intel_dp->train_set[lane] =
intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
--
2.32.0
next prev parent reply other threads:[~2021-10-04 17:11 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 17:05 [Intel-gfx] [PATCH v2 0/5] drm/i915: Improve DP link training further Ville Syrjala
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 1/5] drm/i915: Tweak the DP "max vswing reached?" condition Ville Syrjala
2021-10-06 15:44 ` Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 2/5] drm/i915: Show LTTPR in the TPS debug print Ville Syrjala
2021-10-06 15:47 ` Imre Deak
2021-10-04 17:05 ` Ville Syrjala [this message]
2021-10-06 15:50 ` [Intel-gfx] [PATCH v2 3/5] drm/i915: Print the DP vswing adjustment request Imre Deak
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 4/5] drm/i915: Pimp link training debug prints Ville Syrjala
2021-10-06 16:09 ` Imre Deak
2021-10-06 16:48 ` Ville Syrjälä
2021-10-06 19:28 ` Ville Syrjälä
2021-10-04 17:05 ` [Intel-gfx] [PATCH v2 5/5] drm/i915: Call intel_dp_dump_link_status() for CR failures Ville Syrjala
2021-10-06 16:12 ` Imre Deak
2021-10-04 18:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev2) Patchwork
2021-10-04 23:46 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve DP link training further (rev3) Patchwork
2021-10-05 12:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev4) Patchwork
2021-10-05 12:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-05 13:42 ` Ville Syrjälä
2021-10-05 14:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve DP link training further (rev5) Patchwork
2021-10-05 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-05 18:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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