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From: Ramalingam C <ramalingam.c@intel.com>
To: dri-devel <dri-devel@lists.freedesktop.org>,
	intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel@ffwll.ch>,
	Matthew Auld <matthew.auld@intel.com>,
	CQ Tang <cq.tang@intel.com>,
	Hellstrom Thomas <thomas.hellstrom@intel.com>,
	Ramalingam C <ramalingam.c@intel.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: [Intel-gfx] [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI
Date: Mon, 11 Oct 2021 21:41:55 +0530	[thread overview]
Message-ID: <20211011161155.6397-15-ramalingam.c@intel.com> (raw)
In-Reply-To: <20211011161155.6397-1-ramalingam.c@intel.com>

Details of the new features getting added as part of DG2 enabling and their
implicit impact on the uAPI.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Daniel Vetter <daniel.vetter@ffwll.ch>
cc: Matthew Auld <matthew.auld@intel.com>
---
 Documentation/gpu/rfc/i915_dg2.rst | 47 ++++++++++++++++++++++++++++++
 Documentation/gpu/rfc/index.rst    |  3 ++
 2 files changed, 50 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_dg2.rst

diff --git a/Documentation/gpu/rfc/i915_dg2.rst b/Documentation/gpu/rfc/i915_dg2.rst
new file mode 100644
index 000000000000..a83ca26cd758
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_dg2.rst
@@ -0,0 +1,47 @@
+====================
+I915 DG2 RFC Section
+====================
+
+Upstream plan
+=============
+Plan to upstream the DG2 enabling is:
+
+* Merge basic HW enabling for DG2(Still without pciid)
+* Merge the 64k support for lmem
+* Merge the flat CCS enabling patches
+* Add the pciid for DG2 and enable the DG2 in CI
+
+
+64K page support for lmem
+=========================
+On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is not supported anymore.
+
+DG2 hw dont support the 64k(lmem) and 4k(smem) pages in the same ppgtt Page table. Refer the
+struct drm_i915_gem_create_ext for the implication of handling the 64k page size.
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+        :functions: drm_i915_gem_create_ext
+
+
+flat CCS support for lmem
+=========================
+Gen 12+ devices support 3D surfaces compression and compression formats. This is
+accomplished by an additional compression control state (CCS) stored for each surface.
+
+Gen 12 devices(TGL and DG1) stores compression state in a separate region of memory.
+It is managed by userspace and has an associated set of userspace managed page tables
+used by hardware for address translation.
+
+In Gen 12.5 devices(XEXPSDV and DG2) Flat CCS is introduced to replace the userspace
+managed AUX pagetable with the flat indexed region of device memory for storing the
+compression state
+
+GOP Driver steals a chunk of memory for the CCS surface corresponding to the entire
+range of local memory. The memory required for the CCS of the entire local memory is
+1/256 of the main local memory. The Gop driver will also program a secure register
+(XEHPSDV_FLAT_CCS_BASE_ADDR 0x4910) with this address value.
+
+So the Total local memory available for driver allocation is Total lmem size - CCS data size
+
+Flat CCS data needs to be cleared when a lmem object is allocated. And CCS data can
+be copied in and out of CCS region through XY_CTRL_SURF_COPY_BLT.
diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst
index 91e93a705230..afb320ed4028 100644
--- a/Documentation/gpu/rfc/index.rst
+++ b/Documentation/gpu/rfc/index.rst
@@ -20,6 +20,9 @@ host such documentation:
 
     i915_gem_lmem.rst
 
+.. toctree::
+    i915_dg2.rst
+
 .. toctree::
 
     i915_scheduler.rst
-- 
2.20.1


  parent reply	other threads:[~2021-10-11 16:10 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-11 16:11 [Intel-gfx] [PATCH 00/14] drm/i915/dg2: Enabling 64k page size and flat ccs Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 01/14] drm/i915: Add has_64k_pages flag Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 02/14] drm/i915/xehpsdv: set min page-size to 64K Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 03/14] drm/i915/xehpsdv: enforce min GTT alignment Ramalingam C
2021-10-13 13:38   ` Daniel Vetter
2021-10-13 14:13     ` Matthew Auld
2021-10-14 13:33       ` Daniel Vetter
2021-10-14 14:21         ` Matthew Auld
2021-10-11 16:11 ` [Intel-gfx] [PATCH 04/14] drm/i915: enforce min page size for scratch Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 05/14] drm/i915/gtt/xehpsdv: move scratch page to system memory Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 06/14] drm/i915/xehpsdv: support 64K GTT pages Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 07/14] drm/i915: Add vm min alignment support Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 08/14] drm/i915/selftests: account for min_alignment in GTT selftests Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 09/14] drm/i915/xehpsdv: implement memory coloring Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 10/14] drm/i915/xehpsdv: Add has_flat_ccs to device info Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 11/14] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 12/14] drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms Ramalingam C
2021-10-11 16:11 ` [Intel-gfx] [PATCH 13/14] drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C
2021-10-13 13:46   ` Daniel Vetter
2021-10-11 16:11 ` Ramalingam C [this message]
2021-10-11 17:08   ` [Intel-gfx] [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI Tang, CQ
2021-10-12  5:23   ` Lucas De Marchi
2021-10-13 13:50   ` Daniel Vetter
2021-10-11 18:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Enabling 64k page size and flat ccs Patchwork
2021-10-11 18:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-11 18:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-13 13:51 ` [Intel-gfx] [PATCH 00/14] " Daniel Vetter

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