public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: [Intel-gfx] [PATCH 1/4] drm/i915/clflush: fixup handling of cache_dirty
Date: Thu, 21 Oct 2021 12:44:07 +0100	[thread overview]
Message-ID: <20211021114410.2437099-1-matthew.auld@intel.com> (raw)

In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.

It looks like intel_user_framebuffer_dirty() can arrive here before the
pages are populated.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index f0435c6feb68..d09365b5eb29 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -20,6 +20,7 @@ static void __do_clflush(struct drm_i915_gem_object *obj)
 {
 	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
 	drm_clflush_sg(obj->mm.pages);
+	obj->cache_dirty = false;
 
 	i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
 }
@@ -115,6 +116,5 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
 		GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
 	}
 
-	obj->cache_dirty = false;
 	return true;
 }
-- 
2.26.3


             reply	other threads:[~2021-10-21 11:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 11:44 Matthew Auld [this message]
2021-10-21 11:44 ` [Intel-gfx] [PATCH 2/4] drm/i915/clflush: disallow on discrete Matthew Auld
2021-10-27 11:23   ` Thomas Hellström
2021-10-21 11:44 ` [Intel-gfx] [PATCH 3/4] drm/i915: move cpu_write_needs_clflush Matthew Auld
2021-10-27 11:29   ` Thomas Hellström
2021-10-21 11:44 ` [Intel-gfx] [PATCH 4/4] drm/i915: stop setting cache_dirty on discrete Matthew Auld
2021-10-27 11:30   ` Thomas Hellström
2021-10-21 14:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/clflush: fixup handling of cache_dirty Patchwork
2021-10-21 14:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-21 14:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-21 17:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-27 11:21 ` [Intel-gfx] [PATCH 1/4] " Thomas Hellström

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211021114410.2437099-1-matthew.auld@intel.com \
    --to=matthew.auld@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=thomas.hellstrom@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox