From: Pekka Paalanen <ppaalanen@gmail.com>
To: Harry Wentland <harry.wentland@amd.com>
Cc: "Cyr, Aric" <Aric.Cyr@amd.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
sebastian@sebastianwick.net
Subject: Re: [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes
Date: Thu, 11 Nov 2021 10:22:37 +0200 [thread overview]
Message-ID: <20211111102237.22e8725c@eldfell> (raw)
In-Reply-To: <c94046bc-a083-278a-c9ec-738716da889d@amd.com>
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On Wed, 10 Nov 2021 10:17:59 -0500
Harry Wentland <harry.wentland@amd.com> wrote:
> On 2021-11-10 06:55, Ville Syrjälä wrote:
> > On Wed, Nov 10, 2021 at 10:49:24AM +0200, Pekka Paalanen wrote:
> >> On Wed, 10 Nov 2021 00:02:16 +0200
> >> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >>
> >>> On Tue, Nov 09, 2021 at 03:47:58PM -0500, Harry Wentland wrote:
> >>>> On 2021-11-08 04:54, Pekka Paalanen wrote:
> >>>>> On Thu, 4 Nov 2021 12:27:56 -0400
> >>>>> Harry Wentland <harry.wentland@amd.com> wrote:
> >>>>>
> >>>>>> On 2021-11-04 04:38, Pekka Paalanen wrote:
> >>>>>>> On Wed, 3 Nov 2021 11:08:13 -0400
> >>>>>>> Harry Wentland <harry.wentland@amd.com> wrote:
> >>>>>>>
> >>>>>>>> On 2021-09-06 17:38, Uma Shankar wrote:
> >>>>>>>>> Existing LUT precision structure is having only 16 bit
> >>>>>>>>> precision. This is not enough for upcoming enhanced hardwares
> >>>>>>>>> and advance usecases like HDR processing. Hence added a new
> >>>>>>>>> structure with 32 bit precision values.
> >>>>>>>>>
> >>>>>>>>> This also defines a new structure to define color lut ranges,
> >>>>>>>>> along with related macro definitions and enums. This will help
> >>>>>>>>> describe multi segmented lut ranges in the hardware.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >>>>>>>>> ---
> >>>>>>>>> include/uapi/drm/drm_mode.h | 58 +++++++++++++++++++++++++++++++++++++
> >>>>>>>>> 1 file changed, 58 insertions(+)
> >>
> >> ...
> >>
> >>>>>> If the framebuffer is not in FP16 the question then becomes how
> >>>>>> the integer pixel values relate to LUT addressing.
> >>>>>
> >>>>> Traditionally, and in any API I've seen (GL, Vulkan), a usual mapping
> >>>>> is to match minimum unsigned integer value to 0.0, and unsigned maximum
> >>>>> integer value to 1.0. This is how things work on the cable too, right?
> >>>>> (Also taking full vs. limited range video signal into account. And
> >>>>> conversion to cable-YUV if that happens.)
> >>>>>
> >>>>> If you want integer format FB values to map to something else, then you
> >>>>> have to tag the FB with that range information, somehow. New UAPI.
> >>>>>
> >>>>
> >>>> On the cable we send integer values, not floating point. AMD HW uses
> >>>> floating point internally, though, and the PWL API defines floating
> >>>> point entries, so on some level we need to be clear what the floating
> >>>> point entries mean. Either we document that to be [0.0, 1.0] or we
> >>>> have some UAPI to define it. I'm leaning toward the latter but have
> >>>> to think about it some more.
> >>>
> >>> As for Intel hw if you have an integer pixel value of 0xff... (with
> >>> however many bits you have with a specific pixel format) it will get
> >>> extended to 0.fff... (to whatever precision the pipe has internally).
> >>> So if we go by that a fixed point 1.0 value in the proposed
> >>> drm_color_lut_range would be considered just outside the gamut. And
> >>> pretty sure fp16 input of 1.0 should also result in a 0.fff... internal
> >>> value as well [1]. I think that definition pretty much matches how GL
> >>> UNORM<->float conversion works as well.
> >>
> >> Does it work that way in GL though?
> >>
> >> I've always thought that with GL_UNSIGNED_BYTE, 0xff maps to 1.0, not
> >> 255.0/256.0.
...
> >
> > That seems to match what I said, or at least tried to say (~0 <-> 1.0 in
> > float). drm_color_lut_range being fixed point would follow the ~0 side of
> > that. Or at least that interpretation would very easily map to our hw.
> >
>
> If I understand you right Intel HW represents 0xff (assuming 8 bpc) as
> the largest (representable) float that is less than 1.0. That float would
> be bigger than 255.0/256.0 but smaller than 256.0/256.0.
I was just really confused and re-reading what Ville wrote originally
now makes sense to me.
So, not what Harry wrote. Let me attempt to reiterate and mark fixed
point hex values with a h to discriminate from float values.
With 8-bit:
0x00 -> 0.000000..0h = 0.0 float
0xff -> 0.ffffff..fh = 1.0 float
Then 1.000..0h is the first value out of range.
Thanks,
pq
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next prev parent reply other threads:[~2021-11-11 8:22 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-06 21:38 [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Uma Shankar
2021-09-06 21:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 21:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline Uma Shankar
2021-10-12 10:30 ` Pekka Paalanen
2021-10-12 10:35 ` Simon Ser
2021-10-12 12:00 ` Pekka Paalanen
2021-10-12 19:11 ` Shankar, Uma
2021-10-13 7:25 ` Pekka Paalanen
2021-10-14 19:46 ` Shankar, Uma
2021-10-12 20:58 ` Shankar, Uma
2021-10-13 8:30 ` Pekka Paalanen
2021-10-14 19:44 ` Shankar, Uma
2021-10-15 7:42 ` Pekka Paalanen
2021-10-26 15:11 ` Harry Wentland
2021-10-26 15:36 ` Harry Wentland
2021-10-27 8:00 ` Pekka Paalanen
2021-10-27 12:48 ` Harry Wentland
2021-10-26 15:40 ` Harry Wentland
2021-11-23 15:05 ` Harry Wentland
2021-11-25 20:43 ` Shankar, Uma
2021-11-26 8:21 ` Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 02/22] drm: Add Enhanced Gamma and color lut range attributes Uma Shankar
2021-11-03 15:08 ` Harry Wentland
2021-11-04 8:38 ` Pekka Paalanen
2021-11-04 16:27 ` Harry Wentland
2021-11-05 11:49 ` Ville Syrjälä
2021-11-09 20:22 ` Harry Wentland
2021-11-08 9:54 ` Pekka Paalanen
2021-11-09 20:47 ` Harry Wentland
2021-11-09 22:02 ` Ville Syrjälä
2021-11-10 8:49 ` Pekka Paalanen
2021-11-10 11:55 ` Ville Syrjälä
2021-11-10 15:17 ` Harry Wentland
2021-11-11 8:22 ` Pekka Paalanen [this message]
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 03/22] drm: Add Plane Degamma Mode property Uma Shankar
2021-10-12 11:50 ` Pekka Paalanen
2021-10-12 21:02 ` Shankar, Uma
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 04/22] drm: Add Plane Degamma Lut property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Uma Shankar
2021-11-03 15:10 ` Harry Wentland
2021-11-05 12:59 ` Ville Syrjälä
2021-11-09 20:19 ` Harry Wentland
2021-11-09 21:45 ` Ville Syrjälä
2021-11-09 21:56 ` Harry Wentland
2021-11-11 15:17 ` Harry Wentland
2021-11-11 16:42 ` Ville Syrjälä
2021-11-11 20:42 ` Shankar, Uma
2021-11-11 21:10 ` Harry Wentland
2021-11-11 21:58 ` Shankar, Uma
2021-11-12 8:37 ` Pekka Paalanen
2021-11-23 14:40 ` Harry Wentland
2021-11-12 14:54 ` Ville Syrjälä
2021-11-16 8:15 ` Pekka Paalanen
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 06/22] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 07/22] drm/i915/xelpd: Enable plane color features Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 08/22] drm/i915/xelpd: Add color capabilities of SDR planes Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 09/22] drm/i915/xelpd: Program Plane Degamma Registers Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 10/22] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 11/22] drm/i915/xelpd: Initialize plane color features Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 12/22] drm/i915/xelpd: Load plane color luts from atomic flip Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 13/22] drm: Add Plane CTM property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 14/22] drm: Add helper to attach Plane ctm property Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 15/22] drm/i915/xelpd: Define Plane CSC Registers Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 16/22] drm/i915/xelpd: Enable Plane CSC Uma Shankar
2021-09-06 21:38 ` [Intel-gfx] [RFC v2 17/22] drm: Add Plane Gamma Mode property Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 18/22] drm: Add Plane Gamma Lut property Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 19/22] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 20/22] drm/i915/xelpd: Add register definitions for Plane Gamma Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 21/22] drm/i915/xelpd: Program Plane Gamma Registers Uma Shankar
2021-09-06 21:39 ` [Intel-gfx] [RFC v2 22/22] drm/i915/xelpd: Enable plane gamma Uma Shankar
2021-09-06 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Add Support for Plane Color Lut and CSC features (rev2) Patchwork
2021-09-06 23:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-12 11:55 ` [Intel-gfx] [RFC v2 00/22] Add Support for Plane Color Lut and CSC features Pekka Paalanen
2021-10-12 21:01 ` Shankar, Uma
2021-10-26 15:02 ` Harry Wentland
2021-10-27 8:18 ` Pekka Paalanen
2022-02-02 16:11 ` Harry Wentland
2022-02-03 17:22 ` Shankar, Uma
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