Re: [Intel-gfx] [PATCH 1/2] drm/i915: Introduce new Tile 4 format

[Imre Deak <imre.deak@intel.com>]

On Thu, Dec 09, 2021 at 05:14:56PM +0200, Chery, Nanley G wrote:
> 
> 
> > -----Original Message-----
> > From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
> > Sent: Thursday, December 9, 2021 5:47 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org; Lisovskiy, Stanislav
> > <stanislav.lisovskiy@intel.com>; Saarinen, Jani <jani.saarinen@intel.com>; C,
> > Ramalingam <ramalingam.c@intel.com>; ville.syrjala@linux.intel.com; Deak,
> > Imre <imre.deak@intel.com>; Chery, Nanley G <nanley.g.chery@intel.com>
> > Subject: [PATCH 1/2] drm/i915: Introduce new Tile 4 format
> > 
> 
> We want this patch to be 2/2, right? That way, we expose public kernel
> support for the format after the kernel gains internal support for it.

Previously modifiers have been added in a separate patch CC'd to
dri-devel (and that patch needs to be before the one starting to use
it) and then merged via the i915 tree only after getting an ACK for this
from Jani or Danvet.

The modifier will be exposed to userspace only after the second
one, so I don't see a problem with that approach.

Either way the patchset looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> With that fixed, this patch is:
> 
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> 
> Alternatively, you could apply the ack to the prior combined patch if you'd like.
> 
> -Nanley
> 
> 
> 
> > This tiling layout uses 4KB tiles in a row-major layout. It has the same shape as
> > Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It only differs from
> > Tile Y at the 256B granularity in between. At this granularity, Tile Y has a shape
> > of 16B x 32 rows, but this tiling has a shape of 64B x 8 rows.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 7f652c96845b..a146c6df1066 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -565,6 +565,17 @@ extern "C" {
> >   */
> >  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> > fourcc_mod_code(INTEL, 8)
> > 
> > +/*
> > + * Intel Tile 4 layout
> > + *
> > + * This is a tiled layout using 4KB tiles in a row-major layout. It has
> > +the same
> > + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x
> > +4). It
> > + * only differs from Tile Y at the 256B granularity in between. At this
> > + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling
> > +has a shape
> > + * of 64B x 8 rows.
> > + */
> > +#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
> > +
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> >   *
> > --
> > 2.24.1.485.gad05a3d8e5
>