From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Drop pointless i830 PIPECONF read
Date: Wed, 2 Feb 2022 13:16:16 +0200 [thread overview]
Message-ID: <20220202111616.1579-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220202111616.1579-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reading the PIPECONF enable bit out from the hardware
in i9xx_set_pipeconf() on i830 is pointless as the bit should
always be set since we keep both pipes constantly running on
i830. Drop the pointless read and just always keep the bit set.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 05713b64d4bc..9e318341a498 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3347,13 +3347,11 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 pipeconf;
-
- pipeconf = 0;
+ u32 pipeconf = 0;
/* we keep both pipes enabled on 830 */
if (IS_I830(dev_priv))
- pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
+ pipeconf |= PIPECONF_ENABLE;
if (crtc_state->double_wide)
pipeconf |= PIPECONF_DOUBLE_WIDE;
--
2.34.1
next prev parent reply other threads:[~2022-02-02 11:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 11:16 [Intel-gfx] [PATCH 1/4] drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section Ville Syrjala
2022-02-02 11:16 ` [Intel-gfx] [PATCH 2/4] drm/i915: Make the pipe/output CSC register writes lockless Ville Syrjala
2022-02-02 11:16 ` [Intel-gfx] [PATCH 3/4] drm/i915: Make the CHV CGM " Ville Syrjala
2022-02-02 11:16 ` Ville Syrjala [this message]
2022-02-02 12:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section Patchwork
2022-02-03 11:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section (rev2) Patchwork
2022-02-04 9:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section (rev3) Patchwork
2022-02-04 10:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-18 12:38 ` [Intel-gfx] [PATCH 1/4] drm/i915: Move PIPE_CHICKEN RMW out from the vblank evade critical section Juha-Pekka Heikkila
2022-02-18 12:45 ` Ville Syrjälä
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