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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915: Populate pipe dbuf slices more accurately during readout
Date: Mon, 7 Feb 2022 09:30:27 +0200	[thread overview]
Message-ID: <20220207073027.GB2471@intel.com> (raw)
In-Reply-To: <20220204141818.1900-2-ville.syrjala@linux.intel.com>

On Fri, Feb 04, 2022 at 04:18:17PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> During readout we cannot assume the planes are actually using the
> slices they are supposed to use. The BIOS may have misprogrammed
> things and put the planes onto the wrong dbuf slices. So let's
> do the readout more carefully to make sure we really know which
> dbuf slices are actually in use by the pipe at the time.

We have actually already bugs, related to this.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2eb70ec38f6e..79d61a2935ea 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6663,6 +6663,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		enum pipe pipe = crtc->pipe;
>  		unsigned int mbus_offset;
>  		enum plane_id plane_id;
> +		u8 slices;
>  
>  		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
>  		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
> @@ -6682,20 +6683,22 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  			skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
>  		}
>  
> -		dbuf_state->slices[pipe] =
> -			skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
> -						dbuf_state->joined_mbus);
> -
>  		dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
>  
>  		/*
>  		 * Used for checking overlaps, so we need absolute
>  		 * offsets instead of MBUS relative offsets.
>  		 */
> -		mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
> +		slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
> +						 dbuf_state->joined_mbus);
> +		mbus_offset = mbus_ddb_offset(dev_priv, slices);
>  		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
>  		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
>  
> +		/* The slices actually used by the planes on the pipe */
> +		dbuf_state->slices[pipe] =
> +			skl_ddb_dbuf_slice_mask(dev_priv, &crtc_state->wm.skl.ddb);
> +
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
>  			    crtc->base.base.id, crtc->base.name,
> -- 
> 2.34.1
> 

  reply	other threads:[~2022-02-07  7:30 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-04 14:18 [Intel-gfx] [PATCH 1/3] drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration Ville Syrjala
2022-02-04 14:18 ` [Intel-gfx] [PATCH 2/3] drm/i915: Populate pipe dbuf slices more accurately during readout Ville Syrjala
2022-02-07  7:30   ` Lisovskiy, Stanislav [this message]
2022-02-04 14:18 ` [Intel-gfx] [PATCH 3/3] drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL Ville Syrjala
2022-02-07  7:30   ` Lisovskiy, Stanislav
2022-02-07  9:45     ` Ville Syrjälä
2022-02-04 15:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration Patchwork
2022-02-04 16:27 ` [Intel-gfx] ✗ Fi.CI.IGT: " Patchwork
2022-02-07  7:29 ` [Intel-gfx] [PATCH 1/3] " Lisovskiy, Stanislav

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