From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 7/8] drm/i915: fixup the initial fb base on DG1
Date: Fri, 4 Mar 2022 17:23:32 +0000 [thread overview]
Message-ID: <20220304172333.991778-8-matthew.auld@intel.com> (raw)
In-Reply-To: <20220304172333.991778-1-matthew.auld@intel.com>
The offset we get looks to be the exact start of DSM, but the
inital_plane_vma expects the address to be relative.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
.../drm/i915/display/intel_plane_initial.c | 22 +++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index f797fcef18fc..b39d3a8dfe45 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -56,10 +56,24 @@ initial_plane_vma(struct drm_i915_private *i915,
if (!mem || plane_config->size == 0)
return NULL;
- base = round_down(plane_config->base,
- I915_GTT_MIN_ALIGNMENT);
- size = round_up(plane_config->base + plane_config->size,
- mem->min_page_size);
+ base = plane_config->base;
+ if (IS_DGFX(i915)) {
+ /*
+ * On discrete the base address should be somewhere in LMEM, but
+ * depending on the size of LMEM the base address might
+ * intersect with the start of DSM, like on DG1, in which case
+ * we need the relative address. In such cases we might also
+ * need to choose between inital fb vs fbc, if space is limited.
+ *
+ * On future discrete HW, like DG2, we should be able to just
+ * allocate directly from LMEM, due to larger LMEM size.
+ */
+ if (base >= i915->dsm.start)
+ base -= i915->dsm.start;
+ }
+
+ size = roundup(base + plane_config->size, mem->min_page_size);
+ base = round_down(base, I915_GTT_MIN_ALIGNMENT);
size -= base;
/*
--
2.34.1
next prev parent reply other threads:[~2022-03-04 17:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-04 17:23 [Intel-gfx] [PATCH 0/8] Some more bits for small BAR enabling Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 1/8] drm/i915/lmem: don't treat small BAR as an error Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 2/8] drm/i915/stolen: " Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 3/8] drm/i915: add i915_gem_object_create_region_at() Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 4/8] drm/i915/buddy: tweak CONTIGUOUS rounding Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 5/8] drm/i915/ttm: wire up the object offset Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 6/8] drm/i915/display: Check mappable aperture when pinning preallocated vma Matthew Auld
2022-03-04 17:23 ` Matthew Auld [this message]
2022-03-04 19:33 ` [Intel-gfx] [PATCH 7/8] drm/i915: fixup the initial fb base on DG1 Ville Syrjälä
2022-03-07 10:32 ` Matthew Auld
2022-03-07 17:06 ` Ville Syrjälä
2022-03-07 18:26 ` Matthew Auld
2022-03-07 18:41 ` Ville Syrjälä
2022-03-07 19:19 ` Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] [PATCH 8/8] drm/i915: fixup the initial fb on DG2 Matthew Auld
2022-03-04 19:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some more bits for small BAR enabling Patchwork
2022-03-04 19:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-04 19:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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