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From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6()
Date: Fri, 11 Mar 2022 12:00:27 -0800	[thread overview]
Message-ID: <20220311200027.33701-1-ashutosh.dixit@intel.com> (raw)

Because VLV_GT_RENDER_RC6 == GEN6_GT_GFX_RC6, the IS_VALLEYVIEW() check is
not needed. Neither is the check present in other code paths which call
intel_rc6_residency_ns() (in functions gen6_drpc(), rc6_residency() and
rc6_residency_ms_show()).

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/i915/i915_pmu.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index cfc21042499d..3e3b09588fd3 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -148,10 +148,7 @@ static u64 __get_rc6(struct intel_gt *gt)
 	struct drm_i915_private *i915 = gt->i915;
 	u64 val;
 
-	val = intel_rc6_residency_ns(&gt->rc6,
-				     IS_VALLEYVIEW(i915) ?
-				     VLV_GT_RENDER_RC6 :
-				     GEN6_GT_GFX_RC6);
+	val = intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6);
 
 	if (HAS_RC6p(i915))
 		val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6p);
-- 
2.34.1


             reply	other threads:[~2022-03-11 20:00 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-11 20:00 Ashutosh Dixit [this message]
2022-03-11 21:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6() Patchwork
2022-03-11 23:51 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-14  5:29 ` [Intel-gfx] [PATCH] " Nilawar, Badal
2022-03-14  9:33 ` Jani Nikula
  -- strict thread matches above, loose matches on Subject: below --
2022-03-14 16:13 Ashutosh Dixit

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