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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add workaround 22014263786
Date: Tue, 19 Apr 2022 07:44:54 -0700	[thread overview]
Message-ID: <20220419144454.173973-2-jose.souza@intel.com> (raw)
In-Reply-To: <20220419144454.173973-1-jose.souza@intel.com>

This workaround fixes screen flickers with FBC.

BSpec: 33450
BSpec: 52890
BSpec: 54369
BSpec: 66624
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 670835318a1f1..b7bdb0739744a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -811,6 +811,14 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc)
 	fbc->funcs->program_cfb(fbc);
 }
 
+static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
+{
+	/* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,dg2,adlp */
+	if (DISPLAY_VER(fbc->i915) >= 11)
+		intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
+			     DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
+}
+
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
 	struct drm_i915_private *i915 = fbc->i915;
@@ -1462,6 +1470,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
 
 	intel_fbc_update_state(state, crtc, plane);
 
+	intel_fbc_program_workarounds(fbc);
 	intel_fbc_program_cfb(fbc);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fef71b242706a..0ec7123197fcb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1400,6 +1400,7 @@
 #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
 #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
 #define   DPFC_CHICKEN_COMP_DUMMY_PIXEL		REG_BIT(14) /* glk+ */
+#define   DPFC_CHICKEN_FORCE_SLB_INVALIDATION	REG_BIT(13) /* icl+ */
 #define   DPFC_DISABLE_DUMMY0			REG_BIT(8) /* ivb+ */
 
 #define GLK_FBC_STRIDE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43228, 0x43268)
-- 
2.35.3


  reply	other threads:[~2022-04-19 14:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-19 14:44 [Intel-gfx] [PATCH 1/2] drm/i915/dg2: Add workaround 18019627453 José Roberto de Souza
2022-04-19 14:44 ` José Roberto de Souza [this message]
2022-04-19 16:37   ` [Intel-gfx] [PATCH 2/2] drm/i915/display: Add workaround 22014263786 Matt Roper
2022-04-19 16:33 ` [Intel-gfx] [PATCH 1/2] drm/i915/dg2: Add workaround 18019627453 Matt Roper
2022-04-19 18:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork
2022-04-19 18:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-20  0:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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