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From: Badal Nilawar <badal.nilawar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: chris@chris-wilson.co.uk
Subject: [Intel-gfx] [RFC] drm/i915/rc6: Access RC6 regs with forcewake
Date: Fri, 22 Apr 2022 19:07:52 +0530	[thread overview]
Message-ID: <20220422133752.1370964-1-badal.nilawar@intel.com> (raw)

To access RC6 related MMIO regs use intel_uncore_write(), which grabs
forcewake if reg requires a forcewake.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index b4770690e794..9edaad3f19b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -55,7 +55,7 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
 
 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
 {
-	intel_uncore_write_fw(uncore, reg, val);
+	intel_uncore_write(uncore, reg, val);
 }
 
 static void gen11_rc6_enable(struct intel_rc6 *rc6)
-- 
2.25.1


             reply	other threads:[~2022-04-22 13:37 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 13:37 Badal Nilawar [this message]
2022-04-22 15:34 ` [Intel-gfx] [RFC] drm/i915/rc6: Access RC6 regs with forcewake Matt Roper
2022-04-25  4:25   ` Nilawar, Badal
2022-04-22 19:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-04-22 23:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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