From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
dri-devel@lists.freedesktop.org,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Dave Airlie <airlied@gmail.com>
Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add first set of DG2 PCI IDs
Date: Mon, 25 Apr 2022 14:12:50 -0700 [thread overview]
Message-ID: <20220425211251.77154-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220425211251.77154-1-matthew.d.roper@intel.com>
The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now (although they'll continue to require force_probe until the
usual requirements are met).
The remaining DG2 IDs for add-in cards will come in a future patch once
some additional required functionality has fully landed.
Bspec: 44477
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
include/drm/i915_pciids.h | 22 ++++++++++++++++++++++
3 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a3a1b4cb2942..1d44f57c2eb0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1058,7 +1058,6 @@ static const struct intel_device_info xehpsdv_info = {
BIT(VECS0) | BIT(VECS1) | \
BIT(VCS0) | BIT(VCS2)
-__maybe_unused
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
XE_LPD_FEATURES,
@@ -1154,6 +1153,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
+ INTEL_DG2_IDS(&dg2_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 74c3ffb66b8d..cefa9ed784ff 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -186,6 +186,18 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
};
+static const u16 subplatform_g10_ids[] = {
+ INTEL_DG2_G10_IDS(0),
+};
+
+static const u16 subplatform_g11_ids[] = {
+ INTEL_DG2_G11_IDS(0),
+};
+
+static const u16 subplatform_g12_ids[] = {
+ INTEL_DG2_G12_IDS(0),
+};
+
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -231,6 +243,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+ } else if (find_devid(devid, subplatform_g10_ids,
+ ARRAY_SIZE(subplatform_g10_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_G10);
+ } else if (find_devid(devid, subplatform_g11_ids,
+ ARRAY_SIZE(subplatform_g11_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_G11);
+ } else if (find_devid(devid, subplatform_g12_ids,
+ ARRAY_SIZE(subplatform_g12_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_G12);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a7b5eea7ffaa..283dadfbb4db 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -692,4 +692,26 @@
INTEL_VGA_DEVICE(0xA7A8, info), \
INTEL_VGA_DEVICE(0xA7A9, info)
+/* DG2 */
+#define INTEL_DG2_G10_IDS(info) \
+ INTEL_VGA_DEVICE(0x5690, info), \
+ INTEL_VGA_DEVICE(0x5691, info), \
+ INTEL_VGA_DEVICE(0x5692, info)
+
+#define INTEL_DG2_G11_IDS(info) \
+ INTEL_VGA_DEVICE(0x5693, info), \
+ INTEL_VGA_DEVICE(0x5694, info), \
+ INTEL_VGA_DEVICE(0x5695, info), \
+ INTEL_VGA_DEVICE(0x56B0, info)
+
+#define INTEL_DG2_G12_IDS(info) \
+ INTEL_VGA_DEVICE(0x5696, info), \
+ INTEL_VGA_DEVICE(0x5697, info), \
+ INTEL_VGA_DEVICE(0x56B2, info)
+
+#define INTEL_DG2_IDS(info) \
+ INTEL_DG2_G10_IDS(info), \
+ INTEL_DG2_G11_IDS(info), \
+ INTEL_DG2_G12_IDS(info)
+
#endif /* _I915_PCIIDS_H */
--
2.35.1
next prev parent reply other threads:[~2022-04-25 21:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 21:12 [Intel-gfx] [PATCH v2 0/3] i915: Upstream initial DG2 PCI IDs Matt Roper
2022-04-25 21:12 ` [Intel-gfx] [PATCH v2 1/3] topic/core-for-CI: Revert DG2 and ATS-M device IDs Matt Roper
2022-04-25 21:12 ` Matt Roper [this message]
2022-04-27 7:01 ` [Intel-gfx] [PATCH v2 2/3] drm/i915: Add first set of DG2 PCI IDs Lucas De Marchi
2022-04-25 21:12 ` [Intel-gfx] [PATCH v2 3/3] topic/core-for-CI: Add remaining DG2 and ATS-M device IDs Matt Roper
2022-04-25 21:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Upstream initial DG2 PCI IDs Patchwork
2022-04-25 21:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-25 22:20 ` Matt Roper
2022-04-26 0:07 ` Vudum, Lakshminarayana
2022-04-25 22:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-26 0:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-04-26 17:06 ` Matt Roper
2022-04-27 5:05 ` Vudum, Lakshminarayana
2022-04-27 4:36 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-04-27 4:53 ` Patchwork
2022-04-28 0:24 ` Matt Roper
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