From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Matthew Auld <matthew.auld@intel.com>,
Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
Date: Tue, 10 May 2022 23:33:03 +0200 [thread overview]
Message-ID: <20220510213304.101055-3-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com>
During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 +-
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..37d23e328bd0c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -13,6 +13,7 @@
#include "i915_gem_mman.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- intel_wakeref_t wakeref;
+ struct intel_gt *gt;
+ int i;
- with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
- intel_gt_invalidate_tlbs(to_gt(i915));
+ for_each_gt(gt, i915, i) {
+ int tmp;
+
+ with_intel_gt_pm_if_awake(gt, tmp)
+ intel_gt_invalidate_tlbs(gt);
+ }
}
return pages;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 2654133b39f22..3b1fbce7ea369 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,7 +55,7 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
for (tmp = 1, intel_gt_pm_get(gt); tmp; \
intel_gt_pm_put(gt), tmp = 0)
-#define with_intel_gt_pm_if_awake(gt, wf) \
+#define with_intel_gt_pm_if_awake(gt, tmp) \
for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \
intel_gt_pm_put(gt), tmp = 0)
--
2.36.0
next prev parent reply other threads:[~2022-05-10 21:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 21:33 [Intel-gfx] [PATCH v2 0/3] Clear TLB caches in all tiles when object is removed Andi Shyti
2022-05-10 21:33 ` [Intel-gfx] [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Andi Shyti
2022-05-10 21:33 ` Andi Shyti [this message]
2022-05-10 21:33 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Andi Shyti
2022-05-10 22:21 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Clear TLB caches in all tiles when object is removed Patchwork
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