From: Matthew Brost <matthew.brost@intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
thomas.hellstrom@intel.com, chris.p.wilson@intel.com,
daniel.vetter@intel.com, christian.koenig@amd.com
Subject: Re: [Intel-gfx] [RFC v3 1/3] drm/doc/rfc: VM_BIND feature design document
Date: Wed, 1 Jun 2022 14:18:49 -0700 [thread overview]
Message-ID: <20220601211849.GA30517@jons-linux-dev-box> (raw)
In-Reply-To: <43746609-4f60-f347-5934-6680516297dd@intel.com>
On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
> > +VM_BIND/UNBIND ioctl will immediately start binding/unbinding the mapping in an
> > +async worker. The binding and unbinding will work like a special GPU engine.
> > +The binding and unbinding operations are serialized and will wait on specified
> > +input fences before the operation and will signal the output fences upon the
> > +completion of the operation. Due to serialization, completion of an operation
> > +will also indicate that all previous operations are also complete.
>
> I guess we should avoid saying "will immediately start binding/unbinding" if
> there are fences involved.
>
> And the fact that it's happening in an async worker seem to imply it's not
> immediate.
>
>
> I have a question on the behavior of the bind operation when no input fence
> is provided. Let say I do :
>
> VM_BIND (out_fence=fence1)
>
> VM_BIND (out_fence=fence2)
>
> VM_BIND (out_fence=fence3)
>
>
> In what order are the fences going to be signaled?
>
> In the order of VM_BIND ioctls? Or out of order?
>
> Because you wrote "serialized I assume it's : in order
>
>
> One thing I didn't realize is that because we only get one "VM_BIND" engine,
> there is a disconnect from the Vulkan specification.
>
> In Vulkan VM_BIND operations are serialized but per engine.
>
> So you could have something like this :
>
> VM_BIND (engine=rcs0, in_fence=fence1, out_fence=fence2)
>
> VM_BIND (engine=ccs0, in_fence=fence3, out_fence=fence4)
>
Question - let's say this done after the above operations:
EXEC (engine=ccs0, in_fence=NULL, out_fence=NULL)
Is the exec ordered with respected to bind (i.e. would fence3 & 4 be
signaled before the exec starts)?
Matt
>
> fence1 is not signaled
>
> fence3 is signaled
>
> So the second VM_BIND will proceed before the first VM_BIND.
>
>
> I guess we can deal with that scenario in userspace by doing the wait
> ourselves in one thread per engines.
>
> But then it makes the VM_BIND input fences useless.
>
>
> Daniel : what do you think? Should be rework this or just deal with wait
> fences in userspace?
>
>
> Sorry I noticed this late.
>
>
> -Lionel
>
>
next prev parent reply other threads:[~2022-06-01 21:25 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 18:32 [Intel-gfx] [RFC v3 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi Niranjana Vishwanathapura
2022-05-17 18:32 ` [Intel-gfx] [RFC v3 1/3] drm/doc/rfc: VM_BIND feature design document Niranjana Vishwanathapura
2022-05-19 22:52 ` Zanoni, Paulo R
2022-05-23 19:05 ` Niranjana Vishwanathapura
2022-05-23 19:08 ` Niranjana Vishwanathapura
2022-05-24 10:08 ` Lionel Landwerlin
2022-06-01 14:25 ` Lionel Landwerlin
2022-06-01 20:28 ` Matthew Brost
2022-06-02 20:11 ` Niranjana Vishwanathapura
2022-06-02 20:35 ` Jason Ekstrand
2022-06-03 7:20 ` Lionel Landwerlin
2022-06-03 23:51 ` Niranjana Vishwanathapura
2022-06-07 17:12 ` Jason Ekstrand
2022-06-07 18:18 ` Niranjana Vishwanathapura
2022-06-07 21:32 ` Niranjana Vishwanathapura
2022-06-08 7:33 ` Tvrtko Ursulin
2022-06-08 21:44 ` Niranjana Vishwanathapura
2022-06-08 21:55 ` Jason Ekstrand
2022-06-08 22:48 ` Niranjana Vishwanathapura
2022-06-09 14:49 ` Lionel Landwerlin
2022-06-09 19:31 ` Niranjana Vishwanathapura
2022-06-10 6:53 ` Lionel Landwerlin
2022-06-10 7:54 ` Niranjana Vishwanathapura
2022-06-10 8:18 ` Lionel Landwerlin
2022-06-10 17:42 ` Niranjana Vishwanathapura
2022-06-13 13:33 ` Zeng, Oak
2022-06-13 18:02 ` Niranjana Vishwanathapura
2022-06-14 7:04 ` Lionel Landwerlin
2022-06-14 17:01 ` Niranjana Vishwanathapura
2022-06-14 21:12 ` Zeng, Oak
2022-06-14 21:47 ` Zeng, Oak
2022-06-01 21:18 ` Matthew Brost [this message]
2022-06-02 5:42 ` Lionel Landwerlin
2022-06-02 16:22 ` Matthew Brost
2022-06-02 20:24 ` Niranjana Vishwanathapura
2022-06-02 20:16 ` Bas Nieuwenhuizen
2022-06-02 2:13 ` Zeng, Oak
2022-06-02 20:48 ` Niranjana Vishwanathapura
2022-06-06 20:45 ` Zeng, Oak
2022-05-17 18:32 ` [Intel-gfx] [RFC v3 2/3] drm/i915: Update i915 uapi documentation Niranjana Vishwanathapura
2022-06-08 11:24 ` Matthew Auld
2022-06-10 1:43 ` Niranjana Vishwanathapura
2022-05-17 18:32 ` [Intel-gfx] [RFC v3 3/3] drm/doc/rfc: VM_BIND uapi definition Niranjana Vishwanathapura
2022-05-19 23:07 ` Zanoni, Paulo R
2022-05-23 19:19 ` Niranjana Vishwanathapura
2022-06-01 9:02 ` Dave Airlie
2022-06-01 9:27 ` Daniel Vetter
2022-06-02 5:08 ` Niranjana Vishwanathapura
2022-06-03 6:53 ` Niranjana Vishwanathapura
2022-06-07 10:42 ` Tvrtko Ursulin
2022-06-07 21:25 ` Niranjana Vishwanathapura
2022-06-08 7:34 ` Tvrtko Ursulin
2022-06-08 19:52 ` Niranjana Vishwanathapura
2022-06-08 6:40 ` Lionel Landwerlin
2022-06-08 6:43 ` Lionel Landwerlin
2022-06-08 8:36 ` Tvrtko Ursulin
2022-06-08 8:45 ` Lionel Landwerlin
2022-06-08 8:54 ` Tvrtko Ursulin
2022-06-08 20:45 ` Niranjana Vishwanathapura
2022-06-15 9:49 ` Tvrtko Ursulin
2022-06-08 7:12 ` Lionel Landwerlin
2022-06-08 21:24 ` Matthew Brost
2022-06-07 10:27 ` Tvrtko Ursulin
2022-06-07 19:37 ` Niranjana Vishwanathapura
2022-06-08 7:17 ` Tvrtko Ursulin
2022-06-08 9:12 ` Matthew Auld
2022-06-08 21:32 ` Niranjana Vishwanathapura
2022-06-09 8:36 ` Matthew Auld
2022-06-09 18:53 ` Niranjana Vishwanathapura
2022-06-10 10:16 ` Tvrtko Ursulin
2022-06-10 10:32 ` Matthew Auld
2022-06-10 8:34 ` Matthew Brost
2022-05-17 20:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/doc/rfc: i915 VM_BIND feature design + uapi (rev3) Patchwork
2022-05-17 20:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-17 21:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-18 2:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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