From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/xehp: Correct steering initialization
Date: Tue, 7 Jun 2022 10:57:16 -0700 [thread overview]
Message-ID: <20220607175716.3338661-1-matthew.d.roper@intel.com> (raw)
Another mistake during the conversion to DSS bitmaps: after retrieving
the DSS ID intel_sseu_find_first_xehp_dss() we forgot to modulo it down
to obtain which ID within the current gslice it is.
Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b7421f109c13..a5c0508c5b63 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1177,8 +1177,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
- WARN_ON(subslice > GEN_DSS_PER_GSLICE);
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
+ GEN_DSS_PER_GSLICE;
__add_mcr_wa(gt, wal, slice, subslice);
--
2.35.3
next reply other threads:[~2022-06-07 19:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 17:57 Matt Roper [this message]
2022-06-08 3:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/xehp: Correct steering initialization Patchwork
2022-06-08 8:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-06-08 14:34 ` Matt Roper
2022-06-08 8:46 ` [Intel-gfx] [PATCH] " Balasubramani Vivekanandan
2022-06-08 20:48 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2022-06-08 22:32 ` Patchwork
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