From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, lucas.demarchi@intel.com, rodrigo.vivi@intel.com
Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/mtl: Add MeteorLake PCI IDs
Date: Thu, 7 Jul 2022 17:03:35 -0700 [thread overview]
Message-ID: <20220708000335.2869311-3-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220708000335.2869311-1-radhakrishna.sripada@intel.com>
Add Meteorlake PCI IDs. Split into M, and P subplatforms.
v2: Update PCI id's
v3: Move id 7d60 under MTL_M(MattR)
Bspec: 55420
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++++++
drivers/gpu/drm/i915/intel_device_info.h | 4 ++++
include/drm/i915_pciids.h | 13 +++++++++++++
5 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 00998a78a2ba..1744036bab10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1019,6 +1019,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ADLP_RPLP(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
+#define IS_METEORLAKE_M(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
+#define IS_METEORLAKE_P(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 859d43c7d0a3..aacc10f2e73f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1214,6 +1214,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_RPLP_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
+ INTEL_MTL_IDS(&mtl_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 27c343316afa..d98fbbd589aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -202,6 +202,14 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(0),
};
+static const u16 subplatform_m_ids[] = {
+ INTEL_MTL_M_IDS(0),
+};
+
+static const u16 subplatform_p_ids[] = {
+ INTEL_MTL_P_IDS(0),
+};
+
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -256,6 +264,12 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_g12_ids,
ARRAY_SIZE(subplatform_g12_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G12);
+ } else if (find_devid(devid, subplatform_m_ids,
+ ARRAY_SIZE(subplatform_m_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_M);
+ } else if (find_devid(devid, subplatform_p_ids,
+ ARRAY_SIZE(subplatform_p_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_P);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 7ba9663213f4..23bf230aa104 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,10 @@ enum intel_platform {
*/
#define INTEL_SUBPLATFORM_N 1
+/* MTL */
+#define INTEL_SUBPLATFORM_M 0
+#define INTEL_SUBPLATFORM_P 1
+
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 1bd0420a213d..278031aa2e84 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -733,5 +733,18 @@
#define INTEL_ATS_M_IDS(info) \
INTEL_ATS_M150_IDS(info), \
INTEL_ATS_M75_IDS(info)
+/* MTL */
+#define INTEL_MTL_M_IDS(info) \
+ INTEL_VGA_DEVICE(0x7D40, info), \
+ INTEL_VGA_DEVICE(0x7D60, info)
+
+#define INTEL_MTL_P_IDS(info) \
+ INTEL_VGA_DEVICE(0x7D45, info), \
+ INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7DD5, info)
+
+#define INTEL_MTL_IDS(info) \
+ INTEL_MTL_M_IDS(info), \
+ INTEL_MTL_P_IDS(info)
#endif /* _I915_PCIIDS_H */
--
2.25.1
next prev parent reply other threads:[~2022-07-08 0:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 0:03 [Intel-gfx] [PATCH v3 0/2] i915: Introduce Meteorlake Radhakrishna Sripada
2022-07-08 0:03 ` [Intel-gfx] [PATCH v3 1/2] drm/i915/mtl: Add MeteorLake platform info Radhakrishna Sripada
2022-07-08 0:21 ` Matt Roper
2022-07-08 0:03 ` Radhakrishna Sripada [this message]
2022-07-08 0:30 ` [Intel-gfx] [PATCH v3 2/2] drm/i915/mtl: Add MeteorLake PCI IDs Matt Roper
2022-07-08 0:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Meteorlake Patchwork
2022-07-08 0:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-07-08 1:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-07-08 16:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-07-08 20:33 ` Matt Roper
2022-07-11 7:09 ` Vudum, Lakshminarayana
2022-07-11 14:27 ` Rodrigo Vivi
2022-07-11 6:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
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