From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/12] drm/i915/gt: Drop a few unused register definitions
Date: Mon, 19 Sep 2022 15:32:50 -0700 [thread overview]
Message-ID: <20220919223259.263525-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220919223259.263525-1-matthew.d.roper@intel.com>
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 559e3473f14c..53bedbd5ba0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -450,13 +450,6 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
-#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
-#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
-
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -963,11 +956,6 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
-#define PMFLUSHDONE_LNICRSDROP (1 << 20)
-#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
-#define PMFLUSHDONE_LNEBLK (1 << 22)
-
#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
@@ -982,9 +970,6 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114)
-#define GEN11_I2M_WRITE_DISABLE (1 << 28)
-
#define GEN8_L3SQCREG4 _MMIO(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
@@ -1179,8 +1164,6 @@
#define SARB_CHICKEN1 _MMIO(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
-
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
--
2.37.3
next prev parent reply other threads:[~2022-09-19 22:33 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 22:32 [Intel-gfx] [PATCH 00/12] Explicit MCR handling and MTL steering Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers Matt Roper
2022-09-26 6:15 ` Balasubramani Vivekanandan
2022-09-28 8:25 ` Balasubramani Vivekanandan
2022-09-19 22:32 ` [Intel-gfx] [PATCH 02/12] drm/i915/xehp: " Matt Roper
2022-09-28 9:50 ` Balasubramani Vivekanandan
2022-09-30 21:54 ` Matt Roper
2022-09-19 22:32 ` Matt Roper [this message]
2022-09-19 22:32 ` [Intel-gfx] [PATCH 04/12] drm/i915/gt: Correct prefix on a few registers Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 05/12] drm/i915/xehp: Check for faults on primary GAM Matt Roper
2022-09-26 12:28 ` Balasubramani Vivekanandan
2022-09-19 22:32 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define MCR registers explicitly Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 07/12] drm/i915/gt: Always use MCR functions on multicast registers Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 08/12] drm/i915/guc: Handle save/restore of MCR registers explicitly Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 09/12] drm/i915/gt: Add MCR-specific workaround initializers Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 10/12] drm/i915: Define multicast registers as a new type Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 11/12] drm/i915/mtl: Add multicast steering for render GT Matt Roper
2022-09-19 22:32 ` [Intel-gfx] [PATCH 12/12] drm/i915/mtl: Add multicast steering for media GT Matt Roper
2022-09-20 0:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering Patchwork
2022-09-20 0:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-20 1:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-20 10:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-20 22:37 ` Matt Roper
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