From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ravi.kumar.vodapalli@intel.com, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 05/14] drm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation
Date: Fri, 30 Sep 2022 17:45:41 -0700 [thread overview]
Message-ID: <20221001004550.3031431-6-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20221001004550.3031431-1-matthew.d.roper@intel.com>
There are cases where we wish to read from any non-terminated MCR
register instance (or the primary instance in the case of GAM ranges),
clear/set some bits, and then write the value back out to the register
in a multicast manner. Adding a "multicast RMW" will avoid the need to
open-code this.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 24 ++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 3 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index a2047a68ea7a..962d3e974384 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -302,6 +302,30 @@ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 va
intel_uncore_write_fw(gt->uncore, reg, value);
}
+/**
+ * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations
+ * @gt: GT structure
+ * @reg: the MCR register to read and write
+ * @clear: bits to clear during RMW
+ * @set: bits to set during RMW
+ *
+ * Performs a read-modify-write on an MCR register in a multicast manner.
+ * This operation only makes sense on MCR registers where all instances are
+ * expected to have the same value. The read will target any non-terminated
+ * instance and the write will be applied to all instances.
+ *
+ * This function assumes the caller is already holding any necessary forcewake
+ * domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should
+ * be obtained automatically.
+ */
+void intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg,
+ u32 clear, u32 set)
+{
+ u32 val = intel_gt_mcr_read_any(gt, reg);
+
+ intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set);
+}
+
/*
* reg_needs_read_steering - determine whether a register read requires
* explicit steering
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 77a8b11c287d..e47e75e66835 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -24,6 +24,9 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt,
void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
i915_reg_t reg, u32 value);
+void intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg,
+ u32 clear, u32 set);
+
void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
i915_reg_t reg,
u8 *group, u8 *instance);
--
2.37.3
next prev parent reply other threads:[~2022-10-01 0:47 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 0:45 [Intel-gfx] [PATCH v2 00/14] Explicit MCR handling and MTL steering Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 01/14] drm/i915/gen8: Create separate reg definitions for new MCR registers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 02/14] drm/i915/xehp: " Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 03/14] drm/i915/gt: Drop a few unused register definitions Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 04/14] drm/i915/gt: Correct prefix on a few registers Matt Roper
2022-10-01 0:45 ` Matt Roper [this message]
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 06/14] drm/i915/xehp: Check for faults on primary GAM Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 07/14] drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw() Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 08/14] drm/i915: Define MCR registers explicitly Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 09/14] drm/i915/gt: Always use MCR functions on multicast registers Matt Roper
2022-10-12 16:18 ` Balasubramani Vivekanandan
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 10/14] drm/i915/guc: Handle save/restore of MCR registers explicitly Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 11/14] drm/i915/gt: Add MCR-specific workaround initializers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 12/14] drm/i915: Define multicast registers as a new type Matt Roper
2022-10-04 12:56 ` Jani Nikula
2022-10-04 13:00 ` Jani Nikula
2022-10-05 1:01 ` Matt Roper
2022-10-13 7:21 ` Balasubramani Vivekanandan
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 13/14] drm/i915/mtl: Add multicast steering for render GT Matt Roper
2022-10-14 16:02 ` Balasubramani Vivekanandan
2022-10-14 22:46 ` Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 14/14] drm/i915/mtl: Add multicast steering for media GT Matt Roper
2022-10-03 8:56 ` Tvrtko Ursulin
2022-10-03 19:32 ` Matt Roper
2022-10-04 10:13 ` Tvrtko Ursulin
2022-10-01 1:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev2) Patchwork
2022-10-01 1:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01 2:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-01 5:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev3) Patchwork
2022-10-01 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01 5:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-01 21:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221001004550.3031431-6-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ravi.kumar.vodapalli@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox