From: Mika Kahola <mika.kahola@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers
Date: Fri, 14 Oct 2022 15:47:23 +0300 [thread overview]
Message-ID: <20221014124740.774835-4-mika.kahola@intel.com> (raw)
In-Reply-To: <20221014124740.774835-1-mika.kahola@intel.com>
Create a separate file to store registers for PICA chips
C10 and C20.
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
new file mode 100644
index 000000000000..dfe156141d73
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_REG_DEFS_H__
+#define __INTEL_CX0_REG_DEFS_H__
+
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3 0x16F640
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4 0x16F840
+#define _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) (_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
+ [PORT_B] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
+ [PORT_TC1] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4) + ((lane) * 4))
+
+#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
+#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
+#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
+#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
+#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
+#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
+
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) + 8)
+#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
+#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
+#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
+#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
+#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
+
+#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
+#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
+#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
+#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
+#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
+#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_END_TIMEOUT 15
+#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
+
+#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
+#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC3 0x16F600
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC4 0x16F800
+#define _XELPDP_PORT_BUF_CTL1(port) (_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_BUF_CTL1_LN0_A, \
+ [PORT_B] = _XELPDP_PORT_BUF_CTL1_LN0_B, \
+ [PORT_TC1] = _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_BUF_CTL1_LN0_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_BUF_CTL1_LN0_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
+
+#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port))
+#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
+#define XELPDP_PORT_REVERSAL REG_BIT(16)
+
+#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
+#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
+#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
+#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
+#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
+#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
+#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
+#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
+#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
+#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
+#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
+
+#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
+#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
+#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
+#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
+#define _XELPDP_PORT_CLOCK_CTL_USBC3 0x16F660
+#define _XELPDP_PORT_CLOCK_CTL_USBC4 0x16F860
+#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_CLOCK_CTL_A, \
+ [PORT_B] = _XELPDP_PORT_CLOCK_CTL_B, \
+ [PORT_TC1] = _XELPDP_PORT_CLOCK_CTL_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_CLOCK_CTL_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_CLOCK_CTL_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_CLOCK_CTL_USBC4))
+
+#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
+#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
+#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
+#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
+#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
+#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
+#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
+#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
+#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
+#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
+#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
+#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
+#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
+#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
+#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
+#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
+#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
+#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
+#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
+#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
+#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
+#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
+
+#endif /* __INTEL_CX0_REG_DEFS_H__ */
--
2.34.1
next prev parent reply other threads:[~2022-10-14 12:52 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup Mika Kahola
2022-11-29 0:23 ` Sripada, Radhakrishna
2022-10-14 12:47 ` [Intel-gfx] [PATCH 02/20] drm/i915/mtl: Add DP rates Mika Kahola
2022-10-14 12:47 ` Mika Kahola [this message]
2022-11-02 16:54 ` [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers Jani Nikula
2022-11-02 16:59 ` Jani Nikula
2022-10-14 12:47 ` [Intel-gfx] [PATCH 04/20] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 05/20] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
2022-10-31 20:29 ` Taylor, Clinton A
2022-11-01 7:31 ` Kahola, Mika
2022-10-14 12:47 ` [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
2022-11-01 2:38 ` Sripada, Radhakrishna
2022-11-15 12:56 ` Kahola, Mika
2022-10-14 12:47 ` [Intel-gfx] [PATCH 08/20] drm/i915/mtl: C20 PLL programming Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 09/20] drm/i915/mtl: C20 HW readout Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 10/20] drm/i915/mtl: C20 port clock calculation Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 11/20] drm/i915/mtl: C20 HDMI state calculations Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 12/20] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 13/20] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 14/20] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 15/20] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 16/20] drm/i915/mtl: Enable TC ports Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 17/20] drm/i915/mtl: MTL PICA hotplug detection Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 18/20] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 19/20] drm/i915/mtl: Power up TCSS Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
2022-10-26 14:26 ` Imre Deak
2022-10-27 8:15 ` Kahola, Mika
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add C10 and C20 phy support Patchwork
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-14 13:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-14 14:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-31 21:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev2) Patchwork
2022-11-01 7:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev3) Patchwork
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