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From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
Date: Tue, 25 Oct 2022 20:16:54 +0000	[thread overview]
Message-ID: <20221025201708.84018-3-umesh.nerlige.ramappa@intel.com> (raw)
In-Reply-To: <20221025201708.84018-1-umesh.nerlige.ramappa@intel.com>

Add new OA formats for DG2.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
  separate series with UMD changes

v3:
- Update commit message to drop 64 bit related description

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> #1
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +++++++
 include/uapi/drm/i915_drm.h      | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 255335868b6a..2b772a6b1cd6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -320,6 +320,8 @@ static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
 	[I915_OA_FORMAT_A12]		    = { 0, 64 },
 	[I915_OA_FORMAT_A12_B8_C8]	    = { 2, 128 },
 	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+	[I915_OAR_FORMAT_A32u40_A4u32_B8_C8]    = { 5, 256 },
+	[I915_OA_FORMAT_A24u40_A14u32_B8_C8]    = { 5, 256 },
 };
 
 #define SAMPLE_OA_REPORT      (1<<0)
@@ -4515,6 +4517,11 @@ static void oa_init_supported_formats(struct i915_perf *perf)
 		oa_format_add(perf, I915_OA_FORMAT_C4_B8);
 		break;
 
+	case INTEL_DG2:
+		oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+		oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+		break;
+
 	default:
 		MISSING_CASE(platform);
 	}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2e613109356b..158b35fb28f3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2666,6 +2666,10 @@ enum drm_i915_oa_format {
 	I915_OA_FORMAT_A12_B8_C8,
 	I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+	/* DG2 */
+	I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+	I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
 	I915_OA_FORMAT_MAX	    /* non-ABI */
 };
 
-- 
2.25.1


  parent reply	other threads:[~2022-10-25 20:17 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-25 20:16 [Intel-gfx] [PATCH v5 00/16] Add DG2 OA support Umesh Nerlige Ramappa
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-10-25 20:16 ` Umesh Nerlige Ramappa [this message]
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 03/16] drm/i915/perf: Fix noa wait predication for DG2 Umesh Nerlige Ramappa
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 05/16] drm/i915/perf: Enable bytes per clock reporting in OA Umesh Nerlige Ramappa
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 06/16] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-10-25 20:16 ` [Intel-gfx] [PATCH v5 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 11/16] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 12/16] drm/i915/perf: Apply Wa_18013179988 Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 13/16] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV Umesh Nerlige Ramappa
2022-10-25 20:17 ` [Intel-gfx] [PATCH v5 16/16] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-10-25 21:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev10) Patchwork
2022-10-25 21:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-26 14:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-26 19:03   ` Umesh Nerlige Ramappa
  -- strict thread matches above, loose matches on Subject: below --
2022-10-18 22:36 [Intel-gfx] [PATCH v5 00/16] Add DG2 OA support Umesh Nerlige Ramappa
2022-10-18 22:36 ` [Intel-gfx] [PATCH v5 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2 Umesh Nerlige Ramappa

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