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From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420
Date: Mon,  7 Nov 2022 13:04:30 +0530	[thread overview]
Message-ID: <20221107073432.1352991-7-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20221107073432.1352991-1-suraj.kandpal@intel.com>

From: Swati Sharma <swati2.sharma@intel.com>

DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy.
If a mode is supported in both RGB and YCbCr420 output
formats by the sink, our policy is to try RGB first and
fall back to YCbCr420, if mode cannot be shown using RGB.
So, to test YCbCr420, we need a debugfs entry (force_dsc_ycbcr420)
to force thisoutput format; so that YCbCr420 code gets executed.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 85 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 86 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfc056a05bbf..2ccaf698cbfb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1770,6 +1770,9 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
+		seq_printf(m, "DSC_YCBCR420_Sink_Support: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)));
 		if (!intel_dp_is_edp(intel_dp))
 			seq_printf(m, "FEC_Sink_Support: %s\n",
 				   str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
@@ -1893,6 +1896,85 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_ycbcr420_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "Force_DSC_YCBCR420_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_ycbcr420_en));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_ycbcr420_write(struct file *file,
+				       const char __user *ubuf,
+				       size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_ycbcr420_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force YCBCR420 for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_ycbcr420_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC YCBCR420 Enable\n",
+		(dsc_ycbcr420_enable) ? "true" : "false");
+	intel_dp->force_dsc_ycbcr420_en = dsc_ycbcr420_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_ycbcr420_open(struct inode *inode,
+				  struct file *file)
+{
+	return single_open(file, i915_dsc_ycbcr420_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_ycbcr420_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_ycbcr420_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_ycbcr420_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1964,6 +2046,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_ycbcr420", 0644, root,
+				    connector, &i915_dsc_ycbcr420_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c6abaaa46e17..4b982a0dadf6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1717,6 +1717,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	bool force_dsc_ycbcr420_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.25.1


  parent reply	other threads:[~2022-11-07  7:36 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14 15:26 [Intel-gfx] [PATCH v4 0/4] Enable YCbCr420 for VDSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 1/4] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 2/4] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 3/4] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-10-14 15:26 ` [Intel-gfx] [PATCH v4 4/4] drm/i915: Fill in native_420 field Suraj Kandpal
2022-10-14 16:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2022-10-14 16:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-14 16:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-14 17:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-17  4:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
2022-10-17  5:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-17 13:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev3) Patchwork
2022-10-17 13:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-17 15:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-18  0:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-19 15:41 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-11-07  7:26 ` [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07  7:26   ` [Intel-gfx] [PATCH v5 8/8] drm/i915: Code styling fixes Suraj Kandpal
2022-11-07  7:34 ` [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07  7:34   ` Suraj Kandpal [this message]
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07  7:34   ` [Intel-gfx] [PATCH v5 8/8] drm/i915: Code styling fixes Suraj Kandpal
2022-11-07  8:30 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable YCbCr420 for VDSC (rev3) Patchwork
2022-11-07  8:46 ` [Intel-gfx] [PATCH 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 2/8] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 3/8] drm/i915: Adding the new registers for DSC Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 4/8] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 5/8] drm/i915: Fill in native_420 field Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs Suraj Kandpal
2022-11-07  8:46   ` [Intel-gfx] [PATCH 8/8] drm/i915: Code styling fixes Suraj Kandpal
  -- strict thread matches above, loose matches on Subject: below --
2022-11-07  7:17 [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:17 ` [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal
2022-11-07  7:39 [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC Suraj Kandpal
2022-11-07  7:39 ` [Intel-gfx] [PATCH v5 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420 Suraj Kandpal

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