From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jonathan.cavitt@intel.com, gregory.f.germano@intel.com,
saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Ensure memory quiesced before invalidation
Date: Tue, 21 Feb 2023 14:13:08 -0800 [thread overview]
Message-ID: <20230221221309.1467995-1-jonathan.cavitt@intel.com> (raw)
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..6f830f80eb0f 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -181,6 +181,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
+ /*
+ * Aux invalidations on Aux CCS platforms require
+ * memory traffic is quiesced prior.
+ */
+ if (!HAS_FLAT_CCS(engine->i915))
+ mode |= EMIT_FLUSH;
+
if (mode & EMIT_FLUSH) {
u32 flags = 0;
u32 *cs;
--
2.25.1
next reply other threads:[~2023-02-21 22:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 22:13 Jonathan Cavitt [this message]
2023-02-21 22:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Poll aux invalidation register bit on invalidation Jonathan Cavitt
2023-02-22 3:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Ensure memory quiesced before invalidation Patchwork
2023-02-22 4:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-03-20 19:41 [Intel-gfx] [PATCH 0/2] Aux invalidation Andi Shyti
2023-03-20 19:41 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Ensure memory quiesced before invalidation Andi Shyti
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